Issue No.06 - November/December (2005 vol.22)
Published by the IEEE Computer Society
Scott Davidson , Sun Microsystems
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/MDT.2005.141
The theme of the 2005 International Test Conference is "Test: Survival of the Fittest." In conjunction with this year's ITC, this special section examines how test helps the fittest of the industry's chips, boards, and systems survive manufacturing to reach its customers. These articles discuss topics such as X-tolerant test response compaction, reducing yield loss using a constrained ATPG, and using IDDQ testing with today's high background currents.
In conjunction with the 2005 International Test Conference, this special section examines how test helps the fittest of the industry's chips, boards, and systems survive manufacturing to reach its customers.
The theme of this year's ITC is "Test: Survival of the Fittest." It is possible to view ITC as a means of selection—perhaps unnatural selection—in several ways: The test methods presented at the conference help weed out components that don't deserve to make it beyond the factory walls. ITC also allows test methodologies to battle it out. Attendees can compare results and choose which techniques should flourish in their laboratories and workstations. The ITC exhibit floor is like an ecosystem, where exhibitors in many niches (ATE, DFT tools, and probe equipment) attempt to attract customer attention. Just as in a real ecosystem, diversity is valuable. There is no one right answer to testing needs, only several answers that might be best for one company and not so good for another.
The first article, "X-Tolerant Test Response Compaction" by Mitra et al., is an entry in the busy field of compression. Xs in the BIST or compression are harmful to fault coverage; this article describes a strategy for making sure that the Xs don't survive, without having to know where they appear in advance.
"A Novel Transition Fault ATPG That Reduces Yield Loss" by Liu describes how to improve the survival rate of good chips by using a constrained ATPG that avoids putting the circuit in illegal states. If this happens, a chip could be rejected for failing a transition test in a situation that could never happen functionally.
The final article, "IC Outlier Identification Using Multiple Test Metrics" by Sabade and Walker, addresses the knotty problem of increasing quality by using IDDQ testing with today's high background currents. Sabade and Walker propose using multiple current ratios, both between measurements within a chip and between neighboring chips on a wafer, to identify chips with suspicious IDDQ profiles.
As you read these articles, I hope you will be moved to think up new means of ensuring that strong electronics products, robust test equipment, and effective test software survive; and that you share these with the test community in the pages of IEEE Design & Test and in the proceedings of future ITCs. Finally, I'd like to thank Editor in Chief Rajesh Gupta and Assistant Editor Anna Kim for helping to bring this special section to fruition.
Scott Davidson is senior staff engineer at Sun Microsystems. His research interests include system test and design for testability. Davidson has a BS from MIT, an MS from the University of Illinois at Urbana-Champaign, and a PhD from the University of Southwestern Louisiana, all in computer science. He is the general vice chair of this year's ITC, program chair of the 2006 IEEE International Workshop on Open Source Test Technology Tools, a member of the Design & Test Editorial Board, and the editor of The Last Byte column. He is a member of the IEEE.