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Issue No.06 - November/December (2005 vol.22)
pp: 548-555
Annie (Yujuan) Zeng , Rensselaer Polytechnic Institute
James (JianQiang) L? , Rensselaer Polytechnic Institute
Kenneth Rose , Rensselaer Polytechnic Institute
Ronald J. Gutmann , Rensselaer Polytechnic Institute
ABSTRACT
The advantages of 3D design can be exploited by reducing the memoryaccess time. In this article, the authors use a simulator based on analyticalmodels to build an optimal processor-memory configuration for two designs:a graphics processor and a microprocessor.
INDEX TERMS
Access time, cycle time, cache performance, wafer-level 3D integration, SRAM, DRAM
CITATION
Annie (Yujuan) Zeng, James (JianQiang) L?, Kenneth Rose, Ronald J. Gutmann, "First-Order Performance Prediction of Cache Memory with Wafer-Level3D Integration", IEEE Design & Test of Computers, vol.22, no. 6, pp. 548-555, November/December 2005, doi:10.1109/MDT.2005.138
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