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Predicting the Performance of a 3D Processor-Memory Chip Stack
November/December 2005 (vol. 22 no. 6)
pp. 540-547
Philip Jacob, Rensselaer Polytechnic Institute
Okan Erdogan, Rensselaer Polytechnic Institute
Aamir Zia, Rensselaer Polytechnic Institute
Paul M. Belemjian, Rensselaer Polytechnic Institute
Russell P. Kraft, Rensselaer Polytechnic Institute
John F. McDonald, Rensselaer Polytechnic Institute
A primary bottleneck in the performance of a processor is in its communication with memory. By allowing the placement of processor and memory in adjacent layers, 3D design provides significant relief, reducing the communication latency. This article studies the impact of 3D design bycomparing the cycles per instruction of such a design with various alternatives.
Index Terms:
Cache memories, Simulation, Performance of Systems
Citation:
Philip Jacob, Okan Erdogan, Aamir Zia, Paul M. Belemjian, Russell P. Kraft, John F. McDonald, "Predicting the Performance of a 3D Processor-Memory Chip Stack," IEEE Design & Test of Computers, vol. 22, no. 6, pp. 540-547, Nov.-Dec. 2005, doi:10.1109/MDT.2005.151
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