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Placement and Routing in 3D Integrated Circuits
November/December 2005 (vol. 22 no. 6)
pp. 520-531
ASCII Text
x 
 
Cristinel Ababei, Yan Feng, Brent Goplen, Hushrav Mogal, Tianpei Zhang, Kia Bazargan, Sachin Sapatnekar, "Placement and Routing in 3D Integrated Circuits," IEEE Design & Test of Computers, vol. 22, no. 6, pp. 520-531, November/December, 2005.
 
 
BibTex
x
 
@article{ 10.1109/MDT.2005.150,
author = {Cristinel Ababei and Yan Feng and Brent Goplen and Hushrav Mogal and Tianpei Zhang and Kia Bazargan and Sachin Sapatnekar},
title = {Placement and Routing in 3D Integrated Circuits},
journal ={IEEE Design & Test of Computers},
volume = {22},
number = {6},
issn = {0740-7475},
year = {2005},
pages = {520-531},
doi = {http://doi.ieeecomputersociety.org/10.1109/MDT.2005.150},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - MGZN
JO - IEEE Design & Test of Computers
TI - Placement and Routing in 3D Integrated Circuits
IS - 6
SN - 0740-7475
SP520
EP531
EPD - 520-531
A1 - Cristinel Ababei,
A1 - Yan Feng,
A1 - Brent Goplen,
A1 - Hushrav Mogal,
A1 - Tianpei Zhang,
A1 - Kia Bazargan,
A1 - Sachin Sapatnekar,
PY - 2005
KW - Placement and routing
KW - VLSI
VL - 22
JA - IEEE Design & Test of Computers
ER -
 
Cristinel Ababei, University of Minnesota
Yan Feng, University of Minnesota
Brent Goplen, University of Minnesota
Hushrav Mogal, University of Minnesota
Tianpei Zhang, University of Minnesota
Kia Bazargan, University of Minnesota
Sachin Sapatnekar, University of Minnesota
Advanced manufacturing and packaging techniques are permitting a glimpse at the near-future, where wires can go in three dimensions, and ICs made in diverse processes can be assembled together--sandwich like--to achieve ever higher levels of integration. This article focuses on a specific CAD problem in connection with 3D ICs: how to partition, place, and wire a design subject to various constraints on power, timing, and manufacturability.
Index Terms:
Placement and routing, VLSI
Citation:
Cristinel Ababei, Yan Feng, Brent Goplen, Hushrav Mogal, Tianpei Zhang, Kia Bazargan, Sachin Sapatnekar, "Placement and Routing in 3D Integrated Circuits," IEEE Design & Test of Computers, vol. 22, no. 6, pp. 520-531, Nov.-Dec. 2005, doi:10.1109/MDT.2005.150
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