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Placement and Routing in 3D Integrated Circuits
November/December 2005 (vol. 22 no. 6)
pp. 520-531
Cristinel Ababei, University of Minnesota
Yan Feng, University of Minnesota
Brent Goplen, University of Minnesota
Hushrav Mogal, University of Minnesota
Tianpei Zhang, University of Minnesota
Kia Bazargan, University of Minnesota
Sachin Sapatnekar, University of Minnesota
Advanced manufacturing and packaging techniques are permitting a glimpse at the near-future, where wires can go in three dimensions, and ICs made in diverse processes can be assembled together--sandwich like--to achieve ever higher levels of integration. This article focuses on a specific CAD problem in connection with 3D ICs: how to partition, place, and wire a design subject to various constraints on power, timing, and manufacturability.
Index Terms:
Placement and routing, VLSI
Cristinel Ababei, Yan Feng, Brent Goplen, Hushrav Mogal, Tianpei Zhang, Kia Bazargan, Sachin Sapatnekar, "Placement and Routing in 3D Integrated Circuits," IEEE Design & Test of Computers, vol. 22, no. 6, pp. 520-531, Nov.-Dec. 2005, doi:10.1109/MDT.2005.150
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