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3D Chip Stack Technology Using Through-Chip Interconnects
November/December 2005 (vol. 22 no. 6)
pp. 512-518
Peter Benkart, Infineon Technologies and University of Ulm
Alexander Kaiser, University of Ulm
Andreas Munding, University of Ulm
Markus Bschorr, University of Ulm
Hans-Joerg Pfleiderer, University of Ulm
Erhard Kohn, University of Ulm
Arne Heittmann, Infineon Technologies
Holger Huebner, Infineon Technologies
Ulrich Ramacher, Infineon Technologies
A key enabler for 3D technologies is the ability to stack chips and buildinterconnects that connect circuitry in different layers of the stack. This articlepresents a technology overview of how to achieve this goal in a 3D fabricationprocess. It also shows measurements for characterizing these interconnects.
Index Terms:
General, Integrated Circuits General
Citation:
Peter Benkart, Alexander Kaiser, Andreas Munding, Markus Bschorr, Hans-Joerg Pfleiderer, Erhard Kohn, Arne Heittmann, Holger Huebner, Ulrich Ramacher, "3D Chip Stack Technology Using Through-Chip Interconnects," IEEE Design & Test of Computers, vol. 22, no. 6, pp. 512-518, Nov.-Dec. 2005, doi:10.1109/MDT.2005.125
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