NOVEMBER/DECEMBER 2005 (Vol. 22, No. 6) pp. 496-497
0740-7475/05/$31.00 © 2005 IEEE
Published by the IEEE Computer Society
Published by the IEEE Computer Society
Guest Editors' Introduction: New Dimensions in 3D Integration
|From 2D to 3D|
|This special issue|
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In the real estate market, it is an often-stated truism that as land becomes more expensive, there is a tendency to build upward, rather than outward. This idea has some resonance in the domain of silicon ICs, where die sizes are limited by yield constraints, among other things. Therefore, there is active interest in moving from the 2D domain of today, which lays out transistors on a single active layer, to 3D design, which stacks several active layers above each other. Moreover, in recent years, interconnects have become a major performance bottleneck, and 3D ICs offer a very attractive alternative to conventional 2D circuits in this context. As across-chip delays move into the range of several clock periods, 3D design shows the potential for significantly reduced interconnect length, delay, and congestion.
From 2D to 3D
Although various forms of 3D fabrication technology have existed for a few decades, only in recent years have several mainstream groups (from academia, government laboratories, and industry) been able to develop highly integrated 3D design technologies that are potentially manufacturable and economically feasible. The move toward 3D design should not be seen as a single drastic move from 2D design, but rather, as a gradual transition. Much of this transitioning is underway and already mainstream, and several companies are marketing 3D structures built by wafer stacking, where the distance between the 3D layers on a wafer are on the order of the wafer thickness. Recent developments in 3D processing technology have resulted in fabrication processes from the Massachusetts Institute of Technology, IBM, and MIT's Lincoln Laboratory, each of which can result in 3D circuits with interlayer thicknesses of about 10 μm; researchers at Lincoln Laboratory, for instance, have recently accepted several university-built designs for fabrication under a MOSIS-like paradigm.
Although 3D technology promises outstanding benefits, it must also surmount several challenges. First, it is essential to exploit the design space to build high-performance systems and architectures to gain the fullest advantage achievable from 3D technologies. Second, there are few commercially available CAD tools for 3D circuit design, and a complete CAD flow is essential to making this technology a reality for industrial designs. The move from 2D to 3D design is, in essence, a topological problem; it is therefore imperative to develop tools that specifically exploit the third dimension to perform tasks such as floorplanning, placement, and routing. Third, a major challenge is the heat that a 3D IC produces given the amount of processing power that it integrates. Dissipating this heat requires novel approaches to thermal management and electrothermal design.
The past few years have seen major strides in the design of 3D circuits. As technologies for 3D design have become more available, research groups have developed architectural techniques and CAD tools to support 3D designs. The objective of this special issue is to provide an overview of various facets of 3D technologies.
This special issue
The issue begins with an overview of 3D technologies in an article by Davis et al. (North Carolina State University), which demystifies 3D ICs by providing a clear and concise description of the technology alternatives, including inductive coupling methods that offer intriguing possibilities in such designs. The authors then describe a design case study for a fast Fourier transform implementation in three dimensions, illustrating the advantages achievable from building such a design and some specific designs implemented in three dimensions.
A major motivator for moving to three dimensions lies in the improvements in the interconnect characteristics. However, building reliable through-chip interconnects is a nontrivial problem, and Benkart et al., in the second article, illustrate the issues involved in silicon processing to build these structures. They discuss methods for characterizing the electrical properties of these structures while also providing an excellent overview of 3D processing.
The next two articles describe CAD techniques for enabling 3D designs: together, they cover FPGAs, standard-cell-based designs, and system-on-package designs. Ababei et al. discuss placement and routing techniques for the first two of these technologies, showing CAD flows for timing-driven partitioning, placement, and routing of FPGAs. They then discuss a place-and-route flow for standard-cell designs that explicitly incorporates thermal analysis and optimization as a design objective. Lim considers physical design issues for system-on-package designs, with a specific focus on thermal optimization and power grid integrity.
In terms of architectural issues, 3D designs offer unique opportunities. For example, while processor speeds have improved dramatically, access times to memory remain a bottleneck in 2D technologies. Allowing process-memory stacking can reduce a significant part of that bottleneck, which is caused by wire latency, yielding potential improvements in speed, bandwidth, power, and memory density. The last three articles describe architectural innovations in the use of 3D techniques to optimize processor-memory communication. Jacob et al. use cycle-accurate simulation techniques to predict the improvements achievable through the use of such topologies. Zeng et al. demonstrate the advantages of a 3D solution in this context for both a graphics processor and a general-purpose microprocessor. Liu et al. consider processor-memory interactions in the context of memory hierarchies, employing techniques such as stream prefetching to manage the requirements for the on-chip level-two and level-three memories.
Collectively, the articles in this special issue provide an excellent snapshot of the state of 3D technology as it stands today. This is clearly not an exhaustive survey, nor did we intend it to be one. We believe these articles will provide the reader with an overview of today's 3D silicon technology in terms of process, CAD, and architectural issues, and a flavor for the open problems that require solutions for the wider proliferation of this technology. There is much more work to be done in this area, and many possibilities remain to be explored. For example, for pin-limited chips, building up becomes more attractive so as to absorb most of the connections "internally" within the 3D chip. For systems with analog or RF functionality, or for sensor systems with integrated processing capabilities, 3D integration provides the ability to place the processing circuitry close to the antenna or sensor (for example, just 5 to 10 μm away, in the next lower layer). Finally, 3D integration provides the potential to build circuits on heterogeneous substrates: for instance, building some layers using CMOS technology and others using gallium arsenide, or by combining semiconductor circuit technology and optical technology. We expect to see future implementations exploit these and other aspects of 3D design.
Sachin Sapatnekar is the Robert and Marjorie Henle Professor in the Department of Electrical and Computer Engineering at the University of Minnesota. His research interests include timing, layout, and 3D integration. Sapatnekar has a BTech from the Indian Institute of Technology, Bombay, an MS from Syracuse University, and a PhD from the University of Illinois, Urbana-Champaign. He has received the NSF Career award, the SRC Technical Excellence award, and best paper awards from the Design Automation Conference and the IEEE International Conference on Computer Design. He is a Fellow of the IEEE and a member of the ACM.
Kevin Nowka is a senior manager of VLSI systems in the IBM Austin Research Laboratory. His research interests include high-performance and low-power circuits, and advanced silicon packaging. Nowka has a BS from Iowa State University and an MS and PhD from Stanford University, all in electrical engineering. He is a member of the IEEE.