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November/December 2005 (vol. 22 no. 6)
pp. 493-494
Rajesh Gupta, Editor in Chief, IEEE Design & Test
3D integration techniques, from wafer stacking to transistors along trench walls in 3D circuits, have existed since the 1980s. Recently, however, new products and platforms?enabled by substantial increases in processing, communications, and storage--have driven major advances in this area. This issue explores the recent advances in 3D integration and discusses the accompanying challenges. The issue also includes a special section of articles selected from the International Test Conference.
Index Terms:
3D integration, vertical stacking, wireless, cell phone, International Test Conference, EDA
Citation:
Rajesh Gupta, "Going 3D: Silicon and D&T," IEEE Design & Test of Computers, vol. 22, no. 6, pp. 493-494, Nov.-Dec. 2005, doi:10.1109/MDT.2005.140
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