Issue No.05 - September/October (2005 vol.22)
Published by the IEEE Computer Society
Grant Martin , Tensilica
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/MDT.2005.121
<em>Comprehensive Functional Verification</em>, by Bruce Wile, John C. Goss, and Wolfgang Roesner (Morgan Kaufmann, 2005, ISBN 0-12-751803-7, 704 pp., $59.95). <p>This new verification book lives up to its title?it is by far one of the most comprehensive books on verification. The authors have structured the volume to first and foremost cover verification as a disciplined methodology, and have placed all the different topics into an overall functional verification cycle. The book is divided into five major parts: an introductory survey of verification; a detailed description of simulation-based dynamic verification; formal verification; verification methodologies and advanced techniques; and case studies.</p>
We've all heard the claim that verification now takes 70% of the time (or, possibly, effort) involved in designing and verifying a complex IC. Although this figure seems more anecdotal than scientific, or possibly based on a survey that is no longer current, it is an indication that the importance of verification has grown in the overall design cycle. Another way of judging its importance is to look at the number of verification books published in the last couple of years: A cursory search of just two publishers found more than 20 verification-related books since 2003. And several books are in the works to come out in the next year. There are books on hardware verification languages (HVLs); on verification methodologies; on verification techniques, such as assertion and transaction-based verification; and now even classic tomes on topics such as testbench writing.
With such a crowded field, there are only a few ways in which a new verification book can stand out. The recent arrival, Comprehensive Functional Verification, by Bruce Wile, John C. Goss, and Wolfgang Roesner, does so by living up to its title—it is by far one of the most comprehensive books on verification. At 704 pages and weighing close to five pounds, it delivers a huge body of material on verification, written from the standpoint of real verification practitioners, all of whom have worked for IBM for many years.
Because verification is a vast topic covering many aspects and subdisciplines, the organization of such an offering is key. The authors have structured the volume to first and foremost cover verification as a disciplined methodology, and have placed all the different topics into an overall functional verification cycle. The book is divided into five major parts: an introductory survey of verification; a detailed description of simulation-based dynamic verification; formal verification; verification methodologies and advanced techniques; and case studies.
Part I contains four chapters that emphasize overall methodologies. Chapter 1 places verification in the context of the chip design process and introduces the verification cycle that underpins the rest of the book. Chapters 2 (on verification flow) and 4 (on the verification plan) cover essential methodology principles and introduce the first hands-on example. Chapter 3 previews topics in dynamic verification, including the basic constructs of stimuli, monitors, checkers, observation categories, assertions, and testbenches.
Part II covers dynamic verification in six chapters, including a chapter on HDLs and simulation engines, which uses VHDL and Verilog as key examples. Chapter 6 focuses on testbenches and coverage, with a brief introduction to HVLs like e, OpenVera, and the SystemC Verification Library. Chapters 7 (on stimulus generation) and 8 (on results checking) are complementary, but the next two chapters go beyond many verification books in dealing with postfabrication verification issues, exploring such topics as system bring-up, hardware debugging, low-power mode verification, and reuse of verification components and system simulation.
In Part III, there is a gratifying and somewhat unusual focus on formal verification methods, which, clearly in the authors' eyes, have entered common verification practice. Chapter 11 introduces both equivalence checking (which has indeed become widely used) and property checking, emphasizing the fundamental concepts underpinning these techniques. Chapter 12 offers a good overview of the Property Specification Language and a discussion of the Open Verification Library, with an extensive discussion of practical application.
Part IV completes the verification cycle in Chapter 13 with discussions on regression, tape-out readiness (answering the question, How do you know when verification has finished? Or, rather, Has enough verification been done?), and escape analysis. Chapter 14 introduces advanced techniques, such as bootstrapping and high-level modeling. Finally, Part V, in one chapter, covers three IBM-based case studies, showing both failures and successes in the verification process and always taking care to draw conclusions for further improvement in future designs.
With close to 700 pages, it is not surprising to find occasional small errors or to find that events in the EDA industry outpace this book's ability to keep up. For example, in Chapter 6, the authors state that Verisity is now under Synopsys; but actually, Cadence acquired Verisity in early 2005. A bigger problem is that the book's references represent a failed attempt to merge all of the chapter references into an integrated whole, which clearly was not done properly. However, a corrected set of references is available on the book's Web site, and an errata page in the book clearly points the reader to the right Web page. Another omission that struck me was apparent in Chapter 5, in the discussion of HDL modeling levels. The book's approach seems based on the modeling taxonomy that Vijay Madisetti and others developed as part of the Rapid Prototyping of Application Specific Signal Processors (Rassp) program in the mid-1990s (which was later enhanced with further development by the Virtual Socket Interface Alliance), but the book gives no reference to this earlier work. Finally, there could have been a little more discussion of SystemVerilog and its relationship to current HDL and HVL approaches, given its likely importance as a major unified Hardware Description and Verification Language (HDVL) in the future. Perhaps some additional judicious editing could have reduced the page count (and weight) of the book to a more manageable level: I can confirm that it is not easy bedtime reading (or lifting).
However, these are small flaws in a book that will prove valuable to the verification practitioner and verification student alike. The hands-on exercises and case studies, and further material available on the Web site, make the book invaluable to anyone teaching functional verification. And much of this material has been tested in courses that the authors have taught to the next generations of verification practitioners. The emphasis on methodologies, concepts, and examples—rather than the details of particular languages—makes the material in this book much more likely to remain valid for the future, no matter what twists and turns in tools and languages occur in the next decade.