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Analysis of Error Recovery Schemes for Networks on Chips
September/October 2005 (vol. 22 no. 5)
pp. 434-442
Srinivasan Murali, Stanford University
Theocharis Theocharides, Pennsylvania State University
N. Vijaykrishnan, Pennsylvania State University
Mary Jane Irwin, Pennsylvania State University
Luca Benini, University of Bologna
Giovanni De Micheli, Ecole Polytechnique Federale de Lausanne
Error resiliency is a must for NoCs, but it must not incur undue costs--particularly in terms of energy consumption. Here, the authors present anauthoritative discussion of the trade-offs involved in various error recoveryschemes, enabling designers to make optimal decisions.
Index Terms:
Performance and Reliability, I/O and Data Communications
Citation:
Srinivasan Murali, Theocharis Theocharides, N. Vijaykrishnan, Mary Jane Irwin, Luca Benini, Giovanni De Micheli, "Analysis of Error Recovery Schemes for Networks on Chips," IEEE Design & Test of Computers, vol. 22, no. 5, pp. 434-442, Sept.-Oct. 2005, doi:10.1109/MDT.2005.104
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