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Æthereal Network on Chip:Concepts, Architectures, and Implementations
September/October 2005 (vol. 22 no. 5)
pp. 414-421
Kees Goossens, Philips Research Laboratories
John Dielissen, Philips Research Laboratories
Andrei Radulescu, Philips Research Laboratories
Many SoC applications require guaranteed levels of service and performance. Can networks on chips (NoCs) enable such guarantees? Here, the authors demonstrate that the ?thereal network can. This particular NoC, developed at Philips Research Laboratories, encompasses hardware, a programming model, and a design flow.
Index Terms:
Network Architecture and Design, Real-time and embedded systems
Citation:
Kees Goossens, John Dielissen, Andrei Radulescu, "Æthereal Network on Chip:Concepts, Architectures, and Implementations," IEEE Design & Test of Computers, vol. 22, no. 5, pp. 414-421, Sept.-Oct. 2005, doi:10.1109/MDT.2005.99
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