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Æthereal Network on Chip:Concepts, Architectures, and Implementations
September/October 2005 (vol. 22 no. 5)
pp. 414-421
ASCII Text
x 
 
Kees Goossens, John Dielissen, Andrei Radulescu, "Æthereal Network on Chip:Concepts, Architectures, and Implementations," IEEE Design & Test of Computers, vol. 22, no. 5, pp. 414-421, September/October, 2005.
 
 
BibTex
x
 
@article{ 10.1109/MDT.2005.99,
author = {Kees Goossens and John Dielissen and Andrei Radulescu},
title = {Æthereal Network on Chip:Concepts, Architectures, and Implementations},
journal ={IEEE Design & Test of Computers},
volume = {22},
number = {5},
issn = {0740-7475},
year = {2005},
pages = {414-421},
doi = {http://doi.ieeecomputersociety.org/10.1109/MDT.2005.99},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - MGZN
JO - IEEE Design & Test of Computers
TI - Æthereal Network on Chip:Concepts, Architectures, and Implementations
IS - 5
SN - 0740-7475
SP414
EP421
EPD - 414-421
A1 - Kees Goossens,
A1 - John Dielissen,
A1 - Andrei Radulescu,
PY - 2005
KW - Network Architecture and Design
KW - Real-time and embedded systems
VL - 22
JA - IEEE Design & Test of Computers
ER -
 
Kees Goossens, Philips Research Laboratories
John Dielissen, Philips Research Laboratories
Andrei Radulescu, Philips Research Laboratories
Many SoC applications require guaranteed levels of service and performance. Can networks on chips (NoCs) enable such guarantees? Here, the authors demonstrate that the ?thereal network can. This particular NoC, developed at Philips Research Laboratories, encompasses hardware, a programming model, and a design flow.
Index Terms:
Network Architecture and Design, Real-time and embedded systems
Citation:
Kees Goossens, John Dielissen, Andrei Radulescu, "Æthereal Network on Chip:Concepts, Architectures, and Implementations," IEEE Design & Test of Computers, vol. 22, no. 5, pp. 414-421, Sept.-Oct. 2005, doi:10.1109/MDT.2005.99
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