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Design, Synthesis, and Test of Networks on Chips
September/October 2005 (vol. 22 no. 5)
pp. 404-413
Partha Pratim Pande, Washington State University
Cristian Grecu, University of British Columbia
Andr? Ivanov, University of British Columbia
Resve Saleh, University of British Columbia
Giovanni De Micheli, Ecole Polytechnique Federale de Lausanne
For networks on chips to succeed as the next generation of on-chip interconnect, researchers must solve the major problems involved in designing, implementing, verifying, and testing them. This article surveys the latest NoC architectures, methods, and tools and shows what must happen to make NoCs part of a viable future.
Index Terms:
VLSI, VLSI Systems, Automatic synthesis, Reliability, Testing, and Fault-Tolerance
Citation:
Partha Pratim Pande, Cristian Grecu, Andr? Ivanov, Resve Saleh, Giovanni De Micheli, "Design, Synthesis, and Test of Networks on Chips," IEEE Design & Test of Computers, vol. 22, no. 5, pp. 404-413, Sept.-Oct. 2005, doi:10.1109/MDT.2005.108
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