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September/October 2005 (vol. 22 no. 5)
pp. 393
Rajesh Gupta, Editor in Chief, IEEE Design & Test
As SoCs continue down the path to smaller geometries and higher integration, their performance measures are changing dramatically. The larger the chip, the greater the disparity between local logic speeds and their interconnect latencies. This issue explores on-silicon integration, discussing challenges in networks on chips, various NoC architectures, the Æthereal NoC, error recovery schemes for NoCs based on packet-switched communication fabrics, and interconnect structures for reconfigurable circuit blocks.
Index Terms:
networks on chips, integration, SoCs, on-chip interconnects
Citation:
Rajesh Gupta, "On-chip networks," IEEE Design & Test of Computers, vol. 22, no. 5, pp. 393, Sept.-Oct. 2005, doi:10.1109/MDT.2005.117
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