Issue No.03 - May/June (2005 vol.22)
Dong Hyun Baik , University of Wisconsin-Madison
Charlie Chung-Ping Chen , University of Wisconsin-Madison
Jeng-Liang Tsai , University of Wisconsin-Madison
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/MDT.2005.75
This article proposes clock skew scheduling as a tool to address causes of performance-related circuit yield loss. It is an interesting example of how managing circuit-level parameters can have a direct impact on yield metrics and, therefore, a clear example of the direction of DFM research.
clock skew scheduling, performance-related circuit yield loss, circuit-level parameters, DFM
Dong Hyun Baik, Charlie Chung-Ping Chen, Jeng-Liang Tsai, "Yield-Driven, False-Path-Aware Clock Skew Scheduling", IEEE Design & Test of Computers, vol.22, no. 3, pp. 214-222, May/June 2005, doi:10.1109/MDT.2005.75