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Issue No.03 - May/June (2005 vol.22)
pp: 200-205
Published by the IEEE Computer Society
Yervant Zorian , Virage Logic
Raul Camposano , Synopsys
Andrzej J. Strojwas , PDF Solutions Inc.
John K. Kibarian , PDF Solutions Inc.
Dennis Wassung , Adams Harkness Inc.
Alex Alexanian , Pont? Solutions Inc.
Steve Wigley , LTX Corp.
Neil Kelly , LTX Corp.
ABSTRACT
Design for manufacturability (DFM) has thus far been the focus of extensive study in the semiconductor industry. Although deep-submicron processes enable the manufacture of area-efficient, high-performance chips, navigating the nanometer landscape presents enormous manufacturability challenges.
Design for manufacturability (DFM) has thus far been the focus of extensive study in the semiconductor industry. Although deep-submicron processes enable the manufacture of area-efficient, high-performance chips, navigating the nanometer landscape presents enormous manufacturability challenges. Basically, nanometer technology results in reduced process yield, reliability, and test quality, deeply affecting time to profit. These drivers are forcing designers to change traditional design flows. At the same time, time-to-market pressures are forcing companies to move into volume production before defect densities reach an acceptable level.
Because of these trends, a company's ability to achieve silicon success at advanced geometries will depend on how quickly it can arrive at working silicon, ensure high yield, and start volume production. This requires the ability to solve most yield-limiting challenges in the presilicon stage or to test, diagnose, and make repairs in a short time. And when you consider that designing a 90-nm chip can cost $25 million or more for nonrecurring engineering costs, designing with silicon-aware blocks and augmenting them with effective manufacturability features becomes crucial.
Optimum yield and reliability at 130-nm technologies and below has become especially challenging with the growing use of complex SoC designs and corresponding IP blocks. To help address this situation, new classes of DFM methods, tools, and IP have emerged. DFM is a set of technologies aimed at improving yield by enhancing communication across the design-manufacturing interface. It includes design techniques and IP that make a product cheaper to produce while maintaining its required quality and/or value. The most commonly used DFM techniques are based on judiciously including manufacturability criteria in the design flow, and can dramatically impact the business performance of chip manufacturers. These techniques can also significantly alter age-old chip design flows.
Major thrusts in DFM
DFM also includes a new class of IP called infrastructure IP. Designers can embed this type of IP into their designs; its sole purpose is to support the SoC's health by performing test, diagnosis, repair, and correction for yield and reliability optimization.
Because of the increasing importance of DFM in complex SoCs, we are dedicating most of this issue of IEEE Design & Test to this topic area. Despite its focus on yield, DFM really a much broader topic, encompassing several areas:

    Design for manufacturable patterns. These techniques include novel design flows based on advanced resolution enhancement techniques (RETs); architecture, logic, circuit, and layout optimization for future lithography nodes; and comparisons between design-rule- versus tool-based DFM methodologies.

    New manufacturability-oriented design blocks. These advanced forms of infrastructure IP are for manufacturability issue detection, analysis, and correction; DFM via adaptive circuits, logic, and architectures; and defect-tolerant designs.

    Improved interaction at the design-manufacturing interface. At the interface between the two, new data preparation flows address the data size explosion problem. Design techniques for reducing mask-related costs are also important.

    Design for yield enhancement. Chips now incorporate embedded diagnosis and debug functions, and built-in process monitors and other features to perform embedded measurement. They are capable of repair analysis and self-reconfiguration, and can supply data to support statistical design, power and performance analysis, and optimization. Other techniques include variability-aware design and behavioral or logic synthesis for manufacturability.

    Domain-specific DFM. Specialized DFM covers analog and mixed-signal circuits, and 3D designs. One particular technique, manufacturable power grids, is useful for adapting the power delivery system to manufacturing-related performance unpredictability.

    Test-oriented DFM. This class of DFM includes techniques for manufacturability improvement via test and DFT, including test-based diagnosis, defect-based testing, failure analysis, and test-based yield learning.

Key interfaces
These techniques can involve multiple industry players and can become ever more complex because they work with three key interfaces. The first is the customer interface; it corresponds to the output of a chip manufacturing facility that ends up at an original equipment manufacturer or systems house that creates a system with a set of chips. From the design standpoint, this interface is important because system design must account for the characteristics of the included chips.
Second, the supplier interface involves chip design and manufacturing houses that have a variety of suppliers. Chip design requires sophisticated EDA tools; in most cases, external suppliers provide and integrate these tools. Manufacturing and testing, on the other hand, require expensive equipment and carefully chosen materials; both come from specialized and sophisticated suppliers. So suppliers are a key interface in a company's ability to deliver high-yielding, high-performance chips.
The third interface, the design-manufacturing interface, is the focus of this issue. This interface is fundamental because it has a strong impact on overall long-term profitability, and thus on the return on investment for chip makers.
A simple yet commonly accepted definition for yield is the average percentage of manufactured chips that meet the design specifications. Based on this definition, profit per wafer depends on the number of chips per wafer, the price at which you sell each chip, the average yield, and the total cost per chip (including manufacturing, packaging, testing, distribution, and other overhead). Clearly, yield can have a very strong impact on profitability, especially when profit margins are small—which is increasingly the case because many markets are becoming price sensitive. Because manufacturers test chips at several value chain stages—wafer level (wafer probe), post-packaging test (final test), and so on—various definitions of yield are possible.
DFM enhances the communication bandwidth across the design-manufacturing interface. In most cases, designers accomplish this by judiciously including manufacturability criteria in the chip design flow. This issue includes three articles that correspond to this definition. The key item to remember is that DFM has a positive impact on the business performance of chip manufacturers.
Current DFM challenges
Unfortunately, current design techniques have several key issues. First, at the top levels of the hierarchy, it is very difficult to predict manufacturability. Second, library cell models are becoming more difficult to use as a single performance predictor, because manufacturing-related effects tend to be most concentrated within signal wiring and power distribution, which reside outside the standard cells. Third, conventional design rules cannot capture all the details of manufacturability information, such as information related to RETs. Device models change too often and are becoming very inaccurate, often remaining highly changeable until the chip is almost fully designed. To exacerbate this trend, re-spins have become more costly because mask costs are escalating, and the amount of mask-related data is exploding.
The use of infrastructure IP for manufacturability has certainly helped improve overall chip yield and accelerated time to volume while reducing test cost. Unfortunately, infrastructure IP does have limitations. The problem lies with the simple fact that designers optimize most infrastructure IP blocks individually, without any special knowledge of the independently developed physical IP provided by IP vendors. That is, designers optimizing the infrastructure IP know nothing about the final implementation of the physical IP, such as memory, logic, or analog, being targeted for design for manufacturability.
In effect, the infrastructure IP is "bolted on" to the physical IP as a means of improving the testability, diagnostics, and repairability of the physical IP cores. Today, because designers must locally optimize infrastructure IP solutions, they have no intimate knowledge of the physical IP's defect history or design, and no way to alter or optimize the infrastructure IP to account for it. The result, as you might expect, is suboptimal manufacturability. Defect densities are improving, but not fast enough to make a meaningful impact on desired yields. Because bolt-on infrastructure IP is not aware of the latest manufacturing problems, it fails to identify defective chips (test escapes) and ships them to users.
What's more, the fact that the infrastructure IP and physical IP are separate entities means that designers must individually manage them and separately integrate them into the design. This slows the design process and can negatively impact desired area, power, and speed, adding lengthy cycles in bringing the design up to working silicon.
Finally, using locally optimized infrastructure IP also compromises the chip's reliability, because SoCs that remain untested for certain errors are more likely to fail in the field. To help ensure optimal yield, acceptable reliability, and superior test quality, you must use an infrastructure IP designed with specific knowledge of the physical IP it supports, as well as the targeted manufacturing process. We call this type of semiconductor IP, featuring a highly tuned and integrated combination of physical and infrastructure IP, silicon aware.
For today's nanometer SoCs, it is an essential solution for optimum manufacturability and maximum yield. To ensure optimal test quality, the silicon-aware IP leverages the intimate details of the physical IP's design to provide a better environment for detection and diagnosis. For design productivity, silicon-aware IP delivers the benefit of being a single source of IP, so designers integrate the physical and infrastructure IP as a single entity produced by a single compiler.
New directions DFM solutions
Past DFM work has only partially solved these problems, so there remains much ongoing research in this area, and this special issue is a subset of that work. The five sidebars contained in this introduction show the vision of key individuals involved in the DFM domain, either as executives, technologists, or analysts. The four articles following this guest editorial go into further detail in explaining novel DFM approaches.
The article by Alfred K. Wong, "Some Thoughts on the Integrated Circuit Design-Manufacture Interface," provides a clear view of two complementary approaches to managing the increasingly complex design-manufacturing interface: restricted design rules and model-based design. The author's straightforward discussion is very timely, because the industry is moving toward a combination of both approaches.
The article by Jeng-Liang Tsai et al., "Yield-Driven, False-Path-Aware Clock Skew Scheduling," addresses causes of performance-related circuit yield loss, using clock skew scheduling as a tool. It is an interesting example of how managing circuit-level parameters directly impacts yield metrics—it offers a clear example of the direction in current DFM research.
The article by Jay Jahangiri and David Abercrombie, "Value-Added Defect Testing Techniques," is intriguing in that it describes advanced DFM-oriented test methods that target defect coverage, yield learning, and cost. The authors argue that testing is useful for more than filtering chips: It can directly help target test patterns, provide DFM tools, and reduce overall costs.
Greg Yeric et al., "Infrastructure for Successful BEOL Yield Ramp, Transfer to Manufacturing, and DFM Characterization at 65 nm and Below," provide an excellent description of DFM test structures intended as infrastructure IP for process monitoring. They also describe the systematic yield loss problem for certain category of blocks and then introduce a method for measuring the causes of yield loss.
In addition to these four DFM articles, this special issue also features a Perspective entitled, "New Test Paradigms for Yield and Manufacturability." Its author, Robert Madge, addresses a wide range of yield challenges and solutions based on test-oriented techniques.
Conclusion
Although brief, we believe this special issue is one more step in adding value to the critical field of DFM. We hope you enjoy it.

Juan-Antonio Carballo is currently a partner in IBM's Venture Capital Group, responsible for semiconductors, EDA, and open systems. He previously led research in the design and manufacture of adaptive communications chips at IBM Research, where he filed more than 20 patents in systems and circuit design, design economics, and design management. Carballo has a BS and an MS in telecommunications engineering from the Universidad Politecnica de Madrid, an MBA from College des Ingenieurs in Paris, and a PhD in electrical engineering from the University of Michigan. He chairs the International Technology Roadmap for Semiconductors design and system drivers chapters, and is the chair elect of the IEEE Committee on Design Automation.

Yervant Zorian is vice president and chief scientist of Virage Logic. He previously was the chief technology advisor of LogicVision and a Distinguished Member of Technical Staff at Bell Labs. Zorian has an MSc in computer engineering from the University of Southern California, a PhD in electrical engineering from McGill University, and an executive MBA from the Wharton School of Business, University of Pennsylvania. He is the IEEE Computer Society vice president for conferences and tutorials, founder and chair of IEEE 1500 Working Group, and a Fellow of the IEEE.
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