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Scalable Processor Instruction Set Extension
March/April 2005 (vol. 22 no. 2)
pp. 136-148
ASCII Text
x 
 
J? Becker, Alexander Thomas, "Scalable Processor Instruction Set Extension," IEEE Design & Test of Computers, vol. 22, no. 2, pp. 136-148, March/April, 2005.
 
 
BibTex
x
 
@article{ 10.1109/MDT.2005.43,
author = {J? Becker and Alexander Thomas},
title = {Scalable Processor Instruction Set Extension},
journal ={IEEE Design & Test of Computers},
volume = {22},
number = {2},
issn = {0740-7475},
year = {2005},
pages = {136-148},
doi = {http://doi.ieeecomputersociety.org/10.1109/MDT.2005.43},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - MGZN
JO - IEEE Design & Test of Computers
TI - Scalable Processor Instruction Set Extension
IS - 2
SN - 0740-7475
SP136
EP148
EPD - 136-148
A1 - J? Becker,
A1 - Alexander Thomas,
PY - 2005
VL - 22
JA - IEEE Design & Test of Computers
ER -
 
J? Becker, University of Karlsruhe
Alexander Thomas, University of Karlsruhe
Editor's note: Coarse-grained reconfigurable platforms are good for parallel data-intensive applications but inefficient for sequential control-dominated code. This article (selected from the best of the SBCCI 2003 papers) explores the integration of the general-purpose, Sparc-compliant Leon processor with the Extreme Processing Platform reconfigurable data path. The integration's goal is to optimize the execution of complex multimedia applications such as MPEG-4.
--Fadi J. Kurdahi, University of California, Irvine
Citation:
J? Becker, Alexander Thomas, "Scalable Processor Instruction Set Extension," IEEE Design & Test of Computers, vol. 22, no. 2, pp. 136-148, March-April 2005, doi:10.1109/MDT.2005.43
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