IEEE DESIGN & TEST of COMPUTERS 2004 Annual Index, Volume 21
NOVEMBER/DECEMBER 2004 (Vol. 21, No. 6) pp. 598-607
0740-7475/04/$31.00 © 2004 IEEE

Published by the IEEE Computer Society
IEEE DESIGN & TEST of COMPUTERS 2004 Annual Index, Volume 21
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Author Index

A

Ababir, M.S., see Mishra, P., Mar.-Apr. 04, pp. 122-131.

Abadir, M.S., and L.-C. Wang. "Guest Editors' Introduction: The Verification and Test of Complex Digital ICs," [intro. to special section] Mar.-Apr. 04, pp. 80-83.

Adir, A., E. Almog, L. Fournier, E. Marcus, M. Rimon, M. Vinov, and A. Ziv. "Genesys-Pro: Innovations in Test Program Generation for Functional Processor Verification," Mar.-Apr. 04, pp. 84-93.

Almog, E., see Adir, A., Mar.-Apr. 04, pp. 84-93.

Ann Luh Hwei-Tsu, see Bin-Hong Lin, Jan.-Feb 04, pp. 34-43.

Antonakopoulos, T., see Varsamou, M., Sept.-Oct 04, pp. 416-428.

Appello, D., A. Fudoli, K. Giarda, and V. Tancorre. "Understanding Yield Losses in Logic Circuits," May-June 04, pp. 208-215.

Ashenden, P.J. "Policies and procedures—who needs them?" [Standards] Mar.-Apr. 04, pp. 157-158.

B

Bayraktaroglu, I., see Ozev, S ., Jan.-Feb 04, pp. 44-55.

Benini, L., see Marchal, P ., Sept.-Oct 04, pp. 378-387.

Berman, V., see Marschner, E ., Sept.-Oct 04, pp. 450-451.

Bhaskar Chatterjee, Manoj Sachdev, and A. Keshavarzi. "DFT for Delay Fault Testing of High-Performance Digital Circuits," May-June 04, pp. 248-258.

Bhatia, R., see Scafidi, C ., Mar.-Apr. 04, pp. 94-101.

Bin-Hong Lin, Hwei-Tsu Ann Luh, and Cheng-Wen Wu. "Efficient and Economical Test Equipment Setup Using Procorrelation," Jan.-Feb 04, pp. 34-43.

Breuer, M.A., S.K. Gupta, and T.M. Mak. "Defect and Error Tolerance in the Presence of Massive Numbers of Defects," May-June 04, pp. 216-227.

Bruni, D., see Marchal, P ., Sept.-Oct 04, pp. 378-387.

C

Carballo, J.-A., and S.R. Nassif. "Impact of Design-Manufacturing Interface on SoC Design Methodologies," May-June 04, pp. 183-191.

Caron, M.-C., see Keezer, D.C ., July-Aug 04, pp. 288-301.

Catthoor, F., see Marchal, P ., Sept.-Oct 04, pp. 378-387.

Chaeseok Im, and Soonhoi Ha. "Energy Optimization for Latency- and Quality-Constrained Video Applications," Sept.-Oct 04, pp. 358-366.

Chakraborty, S., see Maxiaguine, A ., Sept.-Oct 04, pp. 368-377.

Chakradhar, S.T., see Lekatsas, H ., Sept.-Oct 04, pp. 406-415.

Chang Naehyuck, see Hojun Shim, ., Sept.-Oct 04, pp. 388-396.

Chang Tsin-Yuan, see Ming-Jun Hsiao, ., July-Aug 04, pp. 322-330.

Chatterjee Bhaskar, see Bhaskar Chatterjee, ., May-June 04, pp. 248-258.

Cheng, K.-T., see Parthasarathy, G ., Mar.-Apr. 04, pp. 132-143.

Cheng, K.-T., see Mak, T.M ., May-June 04, pp. 241-248.

Cheng-Wen Wu, see Bin-Hong Lin, Jan.-Feb 04, pp. 34-43.

Chen Kuang-Chien, see Chia-Chih Yen, Mar.-Apr. 04, pp. 111-120.

Chen Wei, see Jinan Lou, Jan.-Feb 04, pp. 24-32.

Chia-Chih Yen, Jing-Yang Jou, and Kuang-Chien Chen. "A Divide-and-Conquer-Based Algorithm for Automatic Simulation Vector Generation," Mar.-Apr. 04, pp. 111-120.

Corno, F., E. Sanchez, M.S. Reorda, and G. Squillero. "Automatic Test Program Generation: A Case Study," Mar.-Apr. 04, pp. 102-109.

D

DasGupta Sumit, see Sumit DasGupta, July-Aug 04, pp. 271-273.

Davidson, S. "A practical look at ATPG," [review of Digital Logic Testing and Simulation, 2nd edition (Miczo, A.; 2003)] Sept.-Oct 04, pp. 448-449.

Designs Ashenden, see Ashenden, P.J ., Mar.-Apr. 04, pp. 157-158.

Dutt, N., see Mishra, P ., Mar.-Apr. 04, pp. 122-131.

Dutt, N., see Pasricha, S ., Sept.-Oct 04, pp. 398-405.

E

Eles, P., see Marculescu, R ., Sept.-Oct 04, pp. 354-356.

F

Farahmand, T., see Ou, N ., July-Aug 04, pp. 302-313.

Fournier, L., see Adir, A ., Mar.-Apr. 04, pp. 84-93.

Fudoli, A., see Appello, D ., May-June 04, pp. 208-215.

G

Giarda, K., see Appello, D ., May-June 04, pp. 208-215.

Gibson, J.D., see Scafidi, C ., Mar.-Apr. 04, pp. 94-101.

Gizopoulos, D., see Zorian, Y ., May-June 04, pp. 177-182.

Gomez, J.I., see Marchal, P ., Sept.-Oct 04, pp. 378-387.

Gupta, S.K., see Breuer, M.A ., May-June 04, pp. 216-227.

H

Ha Soonhoi, see Chaeseok Im, Sept.-Oct 04, pp. 358-366.

Henkel, J., see Lekatsas, H ., Sept.-Oct 04, pp. 406-415.

Hill, D., and A.B. Kahng. "Guest Editors' Introduction: RTL to GDSII—From Foilware to Standard Practice," [special section intro.] Jan.-Feb 04, pp. 9-12.

Hojun Shim, Naehyuck Chang, and M. Pedram. "Backlight Power Management Framework for Battery-Operated Multimedia Systems," Sept.-Oct 04, pp. 388-396.

Hsiao Ming-Jun, see Ming-Jun Hsiao, July-Aug 04, pp. 322-330.

Huang, W.-J., see Subhasish Mitra, May-June 04, pp. 228-240.

Huang Jing-Reng, see Ming-Jun Hsiao, July-Aug 04, pp. 322-330.

Hwei-Tsu Ann Luh, see Bin-Hong Lin, Jan.-Feb 04, pp. 34-43.

I

Im Chaeseok, see Chaeseok Im, Sept.-Oct 04, pp. 358-366.

Ivanov, A., F. Lombardi, and C. Metra. "Guest Editors' Introduction: Advances in VLSI Testing at Multi Gpbs Rates," [special section intro.] July-Aug 04, pp. 274-276.

Ivanov, A., see Ou, N ., July-Aug 04, pp. 302-313.

Iyer, M.K., see Parthasarathy, G ., Mar.-Apr. 04, pp. 132-143.

J

Jakkula, V., see Lekatsas, H ., Sept.-Oct 04, pp. 406-415.

Jinan Lou, and Wei Chen. "Crosstalk-Aware Placement," Jan.-Feb 04, pp. 24-32.

Jing-Reng Huang, see Ming-Jun Hsiao, July-Aug 04, pp. 322-330.

Jing-Yang Jou, see Chia-Chih Yen, Mar.-Apr. 04, pp. 111-120.

Jou Jing-Yang, see Chia-Chih Yen, Mar.-Apr. 04, pp. 111-120.

K

Kahng, A.B., see Hill, D ., Jan.-Feb 04, pp. 9-12.

Kaushik Roy, see Sirisantana, N ., Jan.-Feb 04, pp. 56-63.

Kazda, M.A., see Trevillyan, L ., Jan.-Feb 04, pp. 14-22.

Keezer, D.C., D. Minier, and M.-C. Caron. "Multiplexing ATE Channels for Production Testing at 2.5 Gbps," July-Aug 04, pp. 288-301.

Keshavarzi, A., see Bhaskar Chatterjee, May-June 04, pp. 248-258.

Krishnamurthy, N., see Mishra, P ., Mar.-Apr. 04, pp. 122-131.

Krstic, A., see Mak, T.M ., May-June 04, pp. 241-248.

Kuang-Chien Chen, see Chia-Chih Yen, Mar.-Apr. 04, pp. 111-120.

Kung, D., see Trevillyan, L ., Jan.-Feb 04, pp. 14-22.

Kunzli, S., see Maxiaguine, A ., Sept.-Oct 04, pp. 368-377.

Kuo, A., see Ou, N ., July-Aug 04, pp. 302-313.

L

Lekatsas, H., J. Henkel, S.T. Chakradhar, and V. Jakkula. "Cypress: Compression and Encryption of Data and Code for Embedded Multimedia Systems," Sept.-Oct 04, pp. 406-415.

Lin Bin-Hong, see Bin-Hong Lin, Jan.-Feb 04, pp. 34-43.

Lombardi, F., see Ivanov, A ., July-Aug 04, pp. 274-276.

Lou Jinan, see Jinan Lou, Jan.-Feb 04, pp. 24-32.

Luh Hwei-Tsu Ann, see Bin-Hong Lin, Jan.-Feb 04, pp. 34-43.

Luthra, M., see Pasricha, S ., Sept.-Oct 04, pp. 398-405.

M

Magarshack, P. "Revolutionizing Manufacturing Processes in Very Deep-Submicron Designs," May-June 04, p. 181.

Mak, T.M., see Breuer, M.A ., May-June 04, pp. 216-227.

Mak, T.M., A. Krstic, K.-T. Cheng, and Li.-C. Wang. "New Challenges in Delay Testing of Nanometer, Multigigahertz Designs," May-June 04, pp. 241-248.

Mak, T.M., M. Tripp, and A. Meixner. "Testing Gbps Interfaces without a Gigahertz Tester," July-Aug 04, pp. 278-286.

Manoj Sachdev, see Bhaskar Chatterjee, May-June 04, pp. 248-258.

Marchal, P., F. Catthoor, D. Bruni, L. Benini, J.I. Gomez, and L. Pinuel. "Integrated Task Scheduling and Data Assignment for SDRAMs in Dynamic Applications," Sept.-Oct 04, pp. 378-387.

Marculescu, R., and P. Eles. "Guest Editors' Introduction: Designing Real-Time Embedded Multimedia Systems," [special section intro.] Sept.-Oct 04, pp. 354-356.

Marcus, E., see Adir, A ., Mar.-Apr. 04, pp. 84-93.

Marschner, E., and V. Berman. "The Continuing Evolution of EDA Standards," [Standards] Sept.-Oct 04, pp. 450-451.

Maxiaguine, A., S. Chakraborty, S. Kunzli, and L. Thiele. "Evaluating Schedulers for Multimedia Processing on Buffer-Constrained SoC Platforms," Sept.-Oct 04, pp. 368-377.

McCluskey, E.J., see Subhasish Mitra, May-June 04, pp. 228-240.

Meixner, A., see Mak, T.M ., July-Aug 04, pp. 278-286.

Metra, C., see Ivanov, A ., July-Aug 04, pp. 274-276.

Ming-Jun Hsiao, Jing-Reng Huang, and Tsin-Yuan Chang. "A Built-in Parametric Timing Measurement Unit," July-Aug 04, pp. 322-330.

Minier, D., see Keezer, D.C ., July-Aug 04, pp. 288-301.

Mishra, P., N. Dutt, N. Krishnamurthy, and M.S. Ababir. "A Top-Down Methodology for Microprocessor Validation," Mar.-Apr. 04, pp. 122-131.

Mitra Subhasish, see Subhasish Mitra, May-June 04, pp. 228-240.

Mohapatra, S., see Pasricha, S ., Sept.-Oct 04, pp. 398-405.

N

Naehyuck Chang, see Hojun Shim,., Sept.-Oct 04, pp. 388-396.

Nardi, A., and A.L. Sangiovanni-Vincentelli. "Logic Synthesis for Manufacturability," May-June 04, pp. 192-199.

Nassif, S.R., see Carballo, J.-A ., May-June 04, pp. 183-191.

O

Orailoglu, A., see Ozev, S ., Jan.-Feb 04, pp. 44-55.

Ou, N., T. Farahmand, A. Kuo, S. Tabatabaei, and A. Ivanov. "Jitter Models for the Design and Test of Gbps-Speed Serial Interconnects," July-Aug 04, pp. 302-313.

Ozev, S., I. Bayraktaroglu, and A. Orailoglu. "Seamless Test of Digital Components in Mixed-Signal Paths," Jan.-Feb 04, pp. 44-55.

P

Papandreou, N., see Varsamou, M ., Sept.-Oct 04, pp. 416-428.

Parthasarathy, G., M.K. Iyer, K.-T. Cheng, and L.-C. Wang. "Safety Property Verification Using Sequential SAT and Bounded Model Checking," Mar.-Apr. 04, pp. 132-143.

Pasricha, S., M. Luthra, S. Mohapatra, N. Dutt, and N. Venkatasubramanian. "Dynamic Backlight Adaptation for Low-Power Handheld Devices," Sept.-Oct 04, pp. 398-405.

Pedram, M., see Hojun Shim, Sept.-Oct 04, pp. 388-396.

Pinuel, L., see Marchal, P ., Sept.-Oct 04, pp. 378-387.

Puri, R., see Trevillyan, L ., Jan.-Feb 04, pp. 14-22.

R

Reddy, L.N., see Trevillyan, L ., Jan.-Feb 04, pp. 14-22.

Reorda, M.S., see Corno, F ., Mar.-Apr. 04, pp. 102-109.

Rimon, M., see Adir, A ., Mar.-Apr. 04, pp. 84-93.

Roy, A., see Sunter, S ., July-Aug 04, pp. 314-321.

Roy Kaushik, see Sirisantana, N ., Jan.-Feb 04, pp. 56-63.

S

Sachdev Manoj, see Bhaskar Chatterjee, May-June 04, pp. 248-258.

Sanchez, E., see Corno, F ., Mar.-Apr. 04, pp. 102-109.

Sangiovanni-Vincentelli, A.L., see Nardi, A ., May-June 04, pp. 192-199.

Saxena, N.R., see Subhasish Mitra, May-June 04, pp. 228-240.

Scafidi, C., J.D. Gibson, and R. Bhatia. "Validating the Itanium 2 Exception Control Unit: A Unit-Level Approach," Mar.-Apr. 04, pp. 94-101.

Shim Hojun, see Hojun Shim, Sept.-Oct 04, pp. 388-396.

Shoukourian, S., V. Vardanian, and Y. Zorian. "SoC Yield Optimization via an Embedded-Memory Test and Repair Infrastructure," May-June 04, pp. 200-207.

Sirisantana, N., and Kaushik Roy. "Low-Power Design Using Multiple Channel Lengths and Oxide Thicknesses," Jan.-Feb 04, pp. 56-63.

Soonhoi Ha, see Chaeseok Im, Sept.-Oct 04, pp. 358-366.

Squillero, G., see Corno, F ., Mar.-Apr. 04, pp. 102-109.

Subhasish Mitra, W.-J. Huang, N.R. Saxena, S.-Y. Yu, and E.J. McCluskey. "Reconfigurable Architecture for Autonomous Self-Repair," May-June 04, pp. 228-240.

Sumit DasGupta, "Looking back, looking around," [ D&T: 20 Years of Service] July-Aug 04, pp. 271-273.

Sunter, S., and A. Roy. "On-Chip Digital Jitter Measurement, from Megahertz to Gigahertz," July-Aug 04, pp. 314-321.

T

Tabatabaei, S., see Ou, N ., July-Aug 04, pp. 302-313.

Tancorre, V., see Appello, D ., May-June 04, pp. 208-215.

Thiele, L., see Maxiaguine, A ., Sept.-Oct 04, pp. 368-377.

Trevillyan, L., D. Kung, R. Puri, L.N. Reddy, and M.A. Kazda. "An Integrated Environment for Technology Closure of Deep-Submicron IC Designs," Jan.-Feb 04, pp. 14-22.

Tripp, M., see Mak, T.M ., July-Aug 04, pp. 278-286.

Tsin-Yuan Chang, see Ming-Jun Hsiao, July-Aug 04, pp. 322-330.

V

van de Goor, A.J. "An Industrial Evaluation of DRAM Tests," Sept.-Oct 04, pp. 430-440.

Vandenberg, C. "Back to Basics: The IC Industry's Reintegration and Dynamics of a Newly Emergent Full-Chip, Design-for-Manufacturability Infrastructure," May-June 04, p. 180.

Vardanian, V., see Shoukourian, S ., May-June 04, pp. 200-207.

Varsamou, M., N. Papandreou, and T. Antonakopoulos. "From Protocol Models to their Implementation: A Versatile Testing Methodology," Sept.-Oct 04, pp. 416-428.

Venkatasubramanian, N., see Pasricha, S ., Sept.-Oct 04, pp. 398-405.

Vinov, M., see Adir, A ., Mar.-Apr. 04, pp. 84-93.

W

Wang, L.-C., see Abadir, M.S ., Mar.-Apr. 04, pp. 80-83.

Wang, L.-C., see Parthasarathy, G ., Mar.-Apr. 04, pp. 132-143.

Wang, Li.-C., see Mak, T.M ., May-June 04, pp. 241-248.

Wei Chen, see Jinan Lou, ., Jan.-Feb 04, pp. 24-32.

Wu Cheng-Wen, see Bin-Hong Lin, Jan.-Feb 04, pp. 34-43.

Y

Yen Chia-Chih, see Chia-Chih Yen, Mar.-Apr. 04, pp. 111-120.

Yu, S.-Y., see Subhasish Mitra, May-June 04, pp. 228-240.

Z

Ziv, A., see Adir, A ., Mar.-Apr. 04, pp. 84-93.

Zorian, Y., and D. Gizopoulos. "Guest Editors' Introduction: Design for Yield and Reliability," [special issue] May-June 04, pp. 177-182.

Zorian, Y., see Shoukourian, S ., May-June 04, pp. 200-207.

Subject Index

Application specific integrated circuits; cf., Mixed analog-digital integrated circuits; System-on-chip
Automatic test equipment

built-in parametric timing meas. unit. Ming-Jun Hsiao, July-Aug. 04, pp. 322-330.

prod. testing, 2.5 Gbps, MUX ATE channels. Keezer, D.C., July-Aug. 04, pp. 288-301.

Automatic testing; cf., Automatic test pattern generation; Automatic test software
Automatic test pattern generation

book review, Digital Logic Testing and Simulation, 2nd edition (Miczo, A.; 2003). Davidson, S., Sept.-Oct. 04, pp. 448-449.

Automatic test software

efficient and economical test equipt. setup, procorrelation. Bin-Hong Lin, Jan.-Feb. 04, pp. 34-43.

Automation; cf., Social aspects of automation
Battery management systems

backlight power management framework for battery-operated multimedia systems. Hojun Shim, Sept.-Oct. 04, pp. 388-396.

Book reviews

Digital Logic Testing and Simulation, 2nd edition (Miczo, A.; 2003). Davidson, S., Sept.-Oct. 04, pp. 448-449.

Brightness

backlight power management framework for battery-operated multimedia systems. Hojun Shim, Sept.-Oct. 04, pp. 388-396.

dynamic backlight adaptation for low-power handheld devices. Pasricha, S., Sept.-Oct. 04, pp. 398-405.

Calibration

prod. testing, 2.5 Gbps, MUX ATE channels. Keezer, D.C., July-Aug. 04, pp. 288-301.

Circuit analysis computing; cf., Circuit simulation
Circuit CAD; cf., Hardware description languages
Circuit layout; cf., Integrated circuit layout
Circuit optimization

crosstalk-aware placement. Jinan Lou, Jan.-Feb. 04, pp. 24-32.

technol. closure of deep-submicron IC designs, integr. environ. Trevillyan, L., Jan.-Feb. 04, pp. 14-22.

Circuit reliability; cf., Integrated circuit reliability
Circuit simulation

technol. closure of deep-submicron IC designs, integr. environ. Trevillyan, L., Jan.-Feb. 04, pp. 14-22.

Circuit testing; cf., Integrated circuit testing
Clocks

technol. closure of deep-submicron IC designs, integr. environ. Trevillyan, L., Jan.-Feb. 04, pp. 14-22.

CMOS digital integrated circuits

low-power design, multiple channel lengths and oxide thicknesses. Sirisantana, N., Jan.-Feb. 04, pp. 56-63.

CMOSFET logic devices

delay fault testing of high-perform. digital ccts., DFT. Bhaskar Chatterjee, May-June 04, pp. 248-258.

CMOS integrated circuits; cf., CMOS digital integrated circuits
Complexity theory

automatic simul. vector gener., divide-and-conquer-based algm. Chia-Chih Yen, Mar.-Apr. 04, pp. 111-120.

safety property verification, seq. SAT and bounded model checking. Parthasarathy, G., Mar.-Apr. 04, pp. 132-143.

validating Itanium 2 exception control unit, unit-level approach. Scafidi, C., Mar.-Apr. 04, pp. 94-101.

Computer applications; cf., Multimedia systems
Computer architecture; cf., Parallel architectures; Reconfigurable architectures
Computerized instrumentation; cf., Automatic test equipment
Computer software; cf., Automatic test software
Crosstalk

crosstalk-aware placement. Jinan Lou, Jan.-Feb. 04, pp. 24-32.

Cryptography

compression and encryption of data and code for embedded multimedia systems. Lekatsas, H., Sept.-Oct. 04, pp. 406-415.

Data compression

compression and encryption of data and code for embedded multimedia systems. Lekatsas, H., Sept.-Oct. 04, pp. 406-415.

Data handling; cf., Electronic data interchange; Exception handling
Design engineering

design for manufacturability (ITC 2003 roundtable). Mar.-Apr. 04, pp. 144-156.

design for yield and reliability (special issue). May-June 04, pp. 177-258.

design for yield and reliability (special issue intro.). Zorian, Y., May-June 04, pp. 177-182.

designing real-time embedded multimedia systems (special section). Sept.-Oct. 04, pp. 354-415.

designing real-time embedded multimedia systems (special section intro.). Marculescu, R., Sept.-Oct. 04, pp. 354-356.

design & test education in Asia (Roundtable). July-Aug. 04, pp. 331-338.

RTL to GDSII, foilware to standard practice (special section). Jan.-Feb. 04, pp. 9-32.

RTL to GDSII, foilware to standard practice (special section intro.). Hill, D., Jan.-Feb. 04, pp. 9-12.

Design engineering; cf., Design for testability
Design for testability

delay fault testing of high-perform. digital ccts., DFT. Bhaskar Chatterjee, May-June 04, pp. 248-258.

delay testing of nanometer, multigigahertz designs, challenges. Mak, T.M., May-June 04, pp. 241-248.

Design methodology

basics, back. Vandenberg, C., May-June 04, p. 180.

design-mfg. interface, SoC design methodologies, impact. Carballo, J.-A., May-June 04, pp. 183-191.

manufacturability, logic synthesis. Nardi, A., May-June 04, pp. 192-199.

very deep-submicron designs, revolutionizing mfg. procs. Magarshack, P., May-June 04, p. 181.

Design of experiments

protocol models to their implementation, a testing methodology. Varsamou, M., Sept.-Oct. 04, pp. 416-428.

Diffusion; cf., Electromigration
Digital circuits; cf., Digital integrated circuits
Digital integrated circuits

functional verification and testbench generation (special section). Mar.-Apr. 04, pp. 80-143.

functional verification and testbench generation (special section intro.). Abadir, M.S., Mar.-Apr. 04, pp. 80-83.

megahertz, gigahertz, on-chip digital jitter meas. Sunter, S., July-Aug. 04, pp. 314-321.

Digital systems; cf., Real-time systems
Display devices; cf., Liquid crystal displays
Distributed memory systems

industrial evaluation of DRAM tests. van de Goor, A.J., Sept.-Oct. 04, pp. 430-440.

DRAM chips

industrial evaluation of DRAM tests. van de Goor, A.J., Sept.-Oct. 04, pp. 430-440.

integrated task scheduling and data assignment for SDRAMs in dynamic applications. Marchal, P., Sept.-Oct. 04, pp. 378-387.

Education

design & test education in Asia (Roundtable). July-Aug. 04, pp. 331-338.

Education; cf., Engineering education
Electrical engineering computing; cf., Automatic test software
Electrical faults; cf., Fault location
Electric field effects; cf., Electromigration
Electric variables measurement; cf., Energy measurement
Electromigration

crosstalk-aware placement. Jinan Lou, Jan.-Feb. 04, pp. 24-32.

Electron device manufacture; cf., Integrated circuit manufacture; Semiconductor device manufacture
Electronic data interchange

continuing evolution of EDA standards. Marschner, E., Sept.-Oct. 04, pp. 450-451.

Electronic engineering; cf., Low-power electronics
Electronic engineering computing; cf., SPICE
Embedded systems

backlight power management framework for battery-operated multimedia systems. Hojun Shim, Sept.-Oct. 04, pp. 388-396.

compression and encryption of data and code for embedded multimedia systems. Lekatsas, H., Sept.-Oct. 04, pp. 406-415.

designing real-time embedded multimedia systems (special section). Sept.-Oct. 04, pp. 354-415.

designing real-time embedded multimedia systems (special section intro.). Marculescu, R., Sept.-Oct. 04, pp. 354-356.

dynamic backlight adaptation for low-power handheld devices. Pasricha, S., Sept.-Oct. 04, pp. 398-405.

energy optim. for latency- and quality-constrained video applications. Chaeseok Im, Sept.-Oct. 04, pp. 358-366.

eval. schedulers for multimedia processing on buffer-constrained SoC platforms. Maxiaguine, A., Sept.-Oct. 04, pp. 368-377.

integrated task scheduling and data assignment for SDRAMs in dynamic applications. Marchal, P., Sept.-Oct. 04, pp. 378-387.

Energy measurement

energy optim. for latency- and quality-constrained video applications. Chaeseok Im, Sept.-Oct. 04, pp. 358-366.

Engineering; cf., Design engineering
Engineering education

design & test education in Asia (Roundtable). July-Aug. 04, pp. 331-338.

interview with A. Richard Newton, engineering applied to societal problems. Sept.-Oct. 04, pp. 441-446.

Error analysis

design and test of Gbps-speed serial interconnects, jitter models. Ou, N., July-Aug. 04, pp. 302-313.

megahertz, gigahertz, on-chip digital jitter meas. Sunter, S., July-Aug. 04, pp. 314-321.

presence of massive nos. of defects, defect and error tolerance. Breuer, M.A., May-June 04, pp. 216-227.

Evolutionary computation; cf., Genetic algorithms
Exception handling

validating Itanium 2 exception control unit, unit-level approach. Scafidi, C., Mar.-Apr. 04, pp. 94-101.

Failure analysis

logic ccts., understanding yield losses. Appello, D., May-June 04, pp. 208-215.

Fault diagnosis; cf., Fault location
Fault location

autonomous self-fix, reconfigurable archit. Subhasish Mitra, May-June 04, pp. 228-240.

Field programmable gate arrays

autonomous self-fix, reconfigurable archit. Subhasish Mitra, May-June 04, pp. 228-240.

Formal logic; cf., Temporal logic
Formal verification

functional verification and testbench generation (special section). Mar.-Apr. 04, pp. 80-143.

functional verification and testbench generation (special section intro.). Abadir, M.S., Mar.-Apr. 04, pp. 80-83.

Functional analysis

functional verification and testbench generation (special section). Mar.-Apr. 04, pp. 80-143.

functional verification and testbench generation (special section intro.). Abadir, M.S., Mar.-Apr. 04, pp. 80-83.

Genetic algorithms

automatic test program gener., case study. Corno, F., Mar.-Apr. 04, pp. 102-109.

Hardware description languages

continuing evolution of EDA standards. Marschner, E., Sept.-Oct. 04, pp. 450-451.

Hardware design languages

automatic test program gener., case study. Corno, F., Mar.-Apr. 04, pp. 102-109.

Genesys-Pro. Adir, A., Mar.-Apr. 04, pp. 84-93

microprocessor validation, top-down methodology. Mishra, P., Mar.-Apr. 04, pp. 122-131.

High-speed techniques

testing at multi Gbps rates (special section). July-Aug. 04, pp. 274-321.

testing at multi Gbps rates (special section intro.). Ivanov, A., July-Aug. 04, pp. 274-276.

History

EDA, Looking back, looking around. Sumit DasGupta, July-Aug. 04, pp. 271-273.

Humanities; cf., History
IEEE standards

continuing evolution of EDA standards. Marschner, E., Sept.-Oct. 04, pp. 450-451.

protocol models to their implementation, a testing methodology. Varsamou, M., Sept.-Oct. 04, pp. 416-428.

standards development, policies and procedures (Standards). Ashenden, P.J., Mar.-Apr. 04, pp. 157-158.

Image processing; cf., Video signal processing
Information technology

interview with A. Richard Newton, engineering applied to societal problems. Sept.-Oct. 04, pp. 441-446.

Instruments; cf., Clocks
Integrated circuit design

crosstalk-aware placement. Jinan Lou, Jan.-Feb. 04, pp. 24-32.

low-power design, multiple channel lengths and oxide thicknesses. Sirisantana, N., Jan.-Feb. 04, pp. 56-63.

technol. closure of deep-submicron IC designs, integr. environ. Trevillyan, L., Jan.-Feb. 04, pp. 14-22.

Integrated circuit design; cf., Integrated circuit layout
Integrated circuit layout

design-mfg. interface, SoC design methodologies, impact. Carballo, J.-A., May-June 04, pp. 183-191.

manufacturability, logic synthesis. Nardi, A., May-June 04, pp. 192-199.

very deep-submicron designs, revolutionizing mfg. procs. Magarshack, P., May-June 04, p. 181.

Integrated circuit manufacture

design-mfg. interface, SoC design methodologies, impact. Carballo, J.-A., May-June 04, pp. 183-191.

efficient and economical test equipt. setup, procorrelation. Bin-Hong Lin, Jan.-Feb. 04, pp. 34-43.

Integrated circuit manufacture; cf., Integrated circuit yield
Integrated circuit reliability

delay fault testing of high-perform. digital ccts., DFT. Bhaskar Chatterjee, May-June 04, pp. 248-258.

design-mfg. interface, SoC design methodologies, impact. Carballo, J.-A., May-June 04, pp. 183-191.

presence of massive nos. of defects, defect and error tolerance. Breuer, M.A., May-June 04, pp. 216-227.

Integrated circuits

design for manufacturability (ITC 2003 roundtable). Mar.-Apr. 04, pp. 144-156.

Integrated circuits; cf., Digital integrated circuits
Integrated circuit testing

delay fault testing of high-perform. digital ccts., DFT. Bhaskar Chatterjee, May-June 04, pp. 248-258.

delay testing of nanometer, multigigahertz designs, challenges. Mak, T.M., May-June 04, pp. 241-248.

digital components, mixed-sig. paths, seamless test. Ozev, S., Jan.-Feb. 04, pp. 44-55.

efficient and economical test equipt. setup, procorrelation. Bin-Hong Lin, Jan.-Feb. 04, pp. 34-43.

presence of massive nos. of defects, defect and error tolerance. Breuer, M.A., May-June 04, pp. 216-227.

prod. testing, 2.5 Gbps, MUX ATE channels. Keezer, D.C., July-Aug. 04, pp. 288-301.

SoC yield optim. via, embedded-memory test and fix infrastructure. Shoukourian, S., May-June 04, pp. 200-207.

Integrated circuit yield

design for yield and reliability (special issue). May-June 04, pp. 177-258.

design for yield and reliability (special issue intro.). Zorian, Y., May-June 04, pp. 177-182.

Integrated memory circuits; cf., DRAM chips
Interference (signal); cf., Crosstalk
Interviews

interview with A. Richard Newton, engineering applied to societal problems. Sept.-Oct. 04, pp. 441-446.

Jitter

design and test of Gbps-speed serial interconnects, jitter models. Ou, N., July-Aug. 04, pp. 302-313.

Languages; cf., Programming languages
Legislation

standards development, policies and procedures (Standards). Ashenden, P.J., Mar.-Apr. 04, pp. 157-158.

Liquid crystal devices; cf., Liquid crystal displays
Liquid crystal displays

backlight power management framework for battery-operated multimedia systems. Hojun Shim, Sept.-Oct. 04, pp. 388-396.

Lithography

basics, back. Vandenberg, C., May-June 04, p. 180.

Logic; cf., Logic design; Logic testing
Logic circuits

understanding yield losses. Appello, D., May-June 04, pp. 208-215.

Logic circuit testing

autonomous self-fix, reconfigurable archit. Subhasish Mitra, May-June 04, pp. 228-240.

ccts., understanding yield losses. Appello, D., May-June 04, pp. 208-215.

delay fault testing of high-perform. digital ccts., DFT. Bhaskar Chatterjee, May-June 04, pp. 248-258.

design and test of Gbps-speed serial interconnects, jitter models. Ou, N., July-Aug. 04, pp. 302-313.

EDA, Looking back, looking around. Sumit DasGupta, July-Aug. 04, pp. 271-273.

gigahertz tester, testing Gbps interfaces. Mak, T.M., July-Aug. 04, pp. 278-286.

megahertz, gigahertz, on-chip digital jitter meas. Sunter, S., July-Aug. 04, pp. 314-321.

presence of massive nos. of defects, defect and error tolerance. Breuer, M.A., May-June 04, pp. 216-227.

prod. testing, 2.5 Gbps, MUX ATE channels. Keezer, D.C., July-Aug. 04, pp. 288-301.

SoC yield optim. via, embedded-memory test and fix infrastructure. Shoukourian, S., May-June 04, pp. 200-207.

validating Itanium 2 exception control unit, unit-level approach. Scafidi, C., Mar.-Apr. 04, pp. 94-101.

Logic design

design and test of Gbps-speed serial interconnects, jitter models. Ou, N., July-Aug. 04, pp. 302-313.

gigahertz tester, testing Gbps interfaces. Mak, T.M., July-Aug. 04, pp. 278-286.

manufacturability, logic synthesis. Nardi, A., May-June 04, pp. 192-199.

validating Itanium 2 exception control unit, unit-level approach. Scafidi, C., Mar.-Apr. 04, pp. 94-101.

Logic devices; cf., Logic circuits
Logic testing

book review; Digital Logic Testing and Simulation, 2nd edition (Miczo, A.; 2003). Davidson, S., Sept.-Oct. 04, pp. 448-449.

Low-power electronics

dynamic backlight adaptation for low-power handheld devices. Pasricha, S., Sept.-Oct. 04, pp. 398-405.

Manufacture

design for manufacturability (ITC 2003 roundtable). Mar.-Apr. 04, pp. 144-156.

Mathematics; cf., Statistics
Mechanical variables measurement; cf., Energy measurement
Microprocessors

automatic test program gener., case study. Corno, F., Mar.-Apr. 04, pp. 102-109.

gigahertz tester, testing Gbps interfaces. Mak, T.M., July-Aug. 04, pp. 278-286.

validating Itanium 2 exception control unit, unit-level approach. Scafidi, C., Mar.-Apr. 04, pp. 94-101.

Mixed analog-digital integrated circuits

digital components, mixed-sig. paths, seamless test. Ozev, S., Jan.-Feb. 04, pp. 44-55.

Mobile communication

dynamic backlight adaptation for low-power handheld devices. Pasricha, S., Sept.-Oct. 04, pp. 398-405.

energy optim. for latency- and quality-constrained video applications. Chaeseok Im, Sept.-Oct. 04, pp. 358-366.

integrated task scheduling and data assignment for SDRAMs in dynamic applications. Marchal, P., Sept.-Oct. 04, pp. 378-387.

MOS digital integrated circuits; cf., CMOS digital integrated circuits
Multimedia servers

eval. schedulers for multimedia processing on buffer-constrained SoC platforms. Maxiaguine, A., Sept.-Oct. 04, pp. 368-377.

Multimedia systems

backlight power management framework for battery-operated multimedia systems. Hojun Shim, Sept.-Oct. 04, pp. 388-396.

compression and encryption of data and code for embedded multimedia systems. Lekatsas, H., Sept.-Oct. 04, pp. 406-415.

designing real-time embedded multimedia systems (special section). Sept.-Oct. 04, pp. 354-415.

designing real-time embedded multimedia systems (special section intro.). Marculescu, R., Sept.-Oct. 04, pp. 354-356.

energy optim. for latency- and quality-constrained video applications. Chaeseok Im, Sept.-Oct. 04, pp. 358-366.

eval. schedulers for multimedia processing on buffer-constrained SoC platforms. Maxiaguine, A., Sept.-Oct. 04, pp. 368-377.

Multiplexing

prod. testing, 2.5 Gbps, MUX ATE channels. Keezer, D.C., July-Aug. 04, pp. 288-301.

testing at multi Gbps rates (special section). July-Aug. 04, pp. 274-321.

testing at multi Gbps rates (special section intro.). Ivanov, A., July-Aug. 04, pp. 274-276.

Multiprocessing systems; cf., Distributed memory systems
Networks (circuits); cf., Integrated circuits; Phase locked loops; Timing circuits
Network servers; cf., Multimedia servers
Network synthesis; cf., Circuit optimization; Integrated circuit design
Notebook computers

backlight power management framework for battery-operated multimedia systems. Hojun Shim, Sept.-Oct. 04, pp. 388-396.

dynamic backlight adaptation for low-power handheld devices. Pasricha, S., Sept.-Oct. 04, pp. 398-405.

Numerical analysis; cf., Error analysis; Functional analysis
Operations research; cf., Scheduling
Optical properties; cf., Brightness
Optimization

energy optim. for latency- and quality-constrained video applications. Chaeseok Im, Sept.-Oct. 04, pp. 358-366.

industrial evaluation of DRAM tests. van de Goor, A.J., Sept.-Oct. 04, pp. 430-440.

Optimization; cf., Circuit optimization; Genetic algorithms
Optimization methods

manufacturability, logic synthesis. Nardi, A., May-June 04, pp. 192-199.

Parallel architectures

automatic test program gener., case study. Corno, F., Mar.-Apr. 04, pp. 102-109.

Parallel processing; cf., Parallel architectures
Performance evaluation

eval. schedulers for multimedia processing on buffer-constrained SoC platforms. Maxiaguine, A., Sept.-Oct. 04, pp. 368-377

industrial evaluation of DRAM tests. van de Goor, A.J., Sept.-Oct. 04, pp. 430-440.

Phase locked loops

built-in parametric timing meas. unit. Ming-Jun Hsiao, July-Aug. 04, pp. 322-330.

megahertz, gigahertz, on-chip digital jitter meas. Sunter, S., July-Aug. 04, pp. 314-321.

Portable computers; cf., Notebook computers
Professional aspects

interview with A. Richard Newton, engineering applied to societal problems. Sept.-Oct. 04, pp. 441-446.

Programmable logic arrays; cf., Field programmable gate arrays
Programming languages

RTL to GDSII, foilware to standard practice (special section). Jan.-Feb. 04, pp. 9-32.

RTL to GDSII, foilware to standard practice (special section intro.). Hill, D., Jan.-Feb. 04, pp. 9-12.

Project engineering; cf., Scheduling
Protocols

protocol models to their implementation, a testing methodology. Varsamou, M., Sept.-Oct. 04, pp. 416-428.

Pulse circuits; cf., Logic circuits
Random-access storage; cf., DRAM chips
Randomized algorithms; cf., Genetic algorithms
Real-time systems

backlight power management framework for battery-operated multimedia systems. Hojun Shim, Sept.-Oct. 04, pp. 388-396.

compression and encryption of data and code for embedded multimedia systems. Lekatsas, H., Sept.-Oct. 04, pp. 406-415.

designing real-time embedded multimedia systems (special section). Sept.-Oct. 04, pp. 354-415.

designing real-time embedded multimedia systems (special section intro.). Marculescu, R., Sept.-Oct. 04, pp. 354-356.

dynamic backlight adaptation for low-power handheld devices. Pasricha, S., Sept.-Oct. 04, pp. 398-405.

energy optim. for latency- and quality-constrained video applications. Chaeseok Im, Sept.-Oct. 04, pp. 358-366.

eval. schedulers for multimedia processing on buffer-constrained SoC platforms. Maxiaguine, A., Sept.-Oct. 04, pp. 368-377.

integrated task scheduling and data assignment for SDRAMs in dynamic applications. Marchal, P., Sept.-Oct. 04, pp. 378-387.

Real-time systems; cf., Embedded systems
Reconfigurable architectures

autonomous self-fix, reconfigurable archit. Subhasish Mitra, May-June 04, pp. 228-240.

Reliability

design for yield and reliability (special issue). May-June 04, pp. 177-258.

design for yield and reliability (special issue intro.). Zorian, Y., May-June 04, pp. 177-182.

Scheduling

eval. schedulers for multimedia processing on buffer-constrained SoC platforms. Maxiaguine, A., Sept.-Oct. 04, pp. 368-377.

integrated task scheduling and data assignment for SDRAMs in dynamic applications. Marchal, P., Sept.-Oct. 04, pp. 378-387.

Search problems; cf., Tree searching
Security of data; cf., Cryptography
Self-testing

autonomous self-fix, reconfigurable archit. Subhasish Mitra, May-June 04, pp. 228-240.

delay testing of nanometer, multigigahertz designs, challenges. Mak, T.M., May-June 04, pp. 241-248.

parametric timing meas. unit. Ming-Jun Hsiao, July-Aug. 04, pp. 322-330.

SoC yield optim. via, embedded-memory test and fix infrastructure. Shoukourian, S., May-June 04, pp. 200-207.

Semiconductor device fabrication

basics, back. Vandenberg, C., May-June 04, p. 180.

Semiconductor device manufacture

design for manufacturability (ITC 2003 roundtable). Mar.-Apr. 04, pp. 144-156.

functional verification and testbench generation (special section). Mar.-Apr. 04, pp. 80-143.

functional verification and testbench generation (special section intro.). Abadir, M.S., Mar.-Apr. 04, pp. 80-83.

Semiconductor devices

integrated task scheduling and data assignment for SDRAMs in dynamic applications. Marchal, P., Sept.-Oct. 04, pp. 378-387.

Sequential logic circuits

safety property verification, seq. SAT and bounded model checking. Parthasarathy, G., Mar.-Apr. 04, pp. 132-143.

Signal processing; cf., Data compression; Video signal processing
Simulation

automatic simul. vector gener., divide-and-conquer-based algm. Chia-Chih Yen, Mar.-Apr. 04, pp. 111-120.

book review; Digital Logic Testing and Simulation, 2nd edition (Miczo, A.; 2003). Davidson, S., Sept.-Oct. 04, pp. 448-449.

Simulation; cf., Circuit simulation
Social and behavioral sciences

interview with A. Richard Newton, engineering applied to societal problems. Sept.-Oct. 04, pp. 441-446.

Social aspects of automation

interview with A. Richard Newton, engineering applied to societal problems. Sept.-Oct. 04, pp. 441-446.

Socio-economic effects; cf., Social aspects of automation
Software engineering; cf., Formal verification
Software requirements and specifications

microprocessor validation, top-down methodology. Mishra, P., Mar.-Apr. 04, pp. 122-131.

Special issues and sections

designing real-time embedded multimedia systems (special section). Sept.-Oct. 04, pp. 354-415.

designing real-time embedded multimedia systems (special section intro.). Marculescu, R., Sept.-Oct. 04, pp. 354-356.

functional verification and testbench generation (special section). Mar.-Apr. 04, pp. 80-143.

functional verification and testbench generation (special section intro.). Abadir, M.S., Mar.-Apr. 04, pp. 80-83.

RTL to GDSII, foilware to standard practice (special section). Jan.-Feb. 04, pp. 9-32.

RTL to GDSII, foilware to standard practice (special section intro.). Hill, D., Jan.-Feb. 04, pp. 9-12.

testing at multi Gbps rates (special section). July-Aug. 04, pp. 274-321.

testing at multi Gbps rates (special section intro.). Ivanov, A., July-Aug. 04, pp. 274-276.

Specification languages; cf., Hardware description languages
SPICE

basics, back. Vandenberg, C., May-June 04, p. 180.

Standards

continuing evolution of EDA standards. Marschner, E., Sept.-Oct. 04, pp. 450-451.

RTL to GDSII, foilware to standard practice (special section). Jan.-Feb. 04, pp. 9-32.

RTL to GDSII, foilware to standard practice (special section intro.). Hill, D., Jan.-Feb. 04, pp. 9-12.

standards development, policies and procedures (Standards). Ashenden, P.J., Mar.-Apr. 04, pp. 157-158.

Standards; cf., IEEE standards; Telecommunication standards
Statistical analysis; cf., Design of experiments
Statistics

delay testing of nanometer, multigigahertz designs, challenges. Mak, T.M., May-June 04, pp. 241-248.

efficient and economical test equipt. setup, procorrelation. Bin-Hong Lin, Jan.-Feb. 04, pp. 34-43.

Switching circuits; cf., Logic circuits
System-on-chip

eval. schedulers for multimedia processing on buffer-constrained SoC platforms. Maxiaguine, A., Sept.-Oct. 04, pp. 368-377.

Systems analysis; cf., Task analysis
Task analysis

integrated task scheduling and data assignment for SDRAMs in dynamic applications. Marchal, P., Sept.-Oct. 04, pp. 378-387.

Telecommunication; cf., Mobile communication; Telecommunication standards
Telecommunication standards

protocol models to their implementation, a testing methodology. Varsamou, M., Sept.-Oct. 04, pp. 416-428.

Telecommunication switching; cf., Multiplexing
Temporal logic

safety property verification, seq. SAT and bounded model checking. Parthasarathy, G., Mar.-Apr. 04, pp. 132-143.

Test equipment

RTL to GDSII, foilware to standard practice (special section). Jan.-Feb. 04, pp. 9-32.

RTL to GDSII, foilware to standard practice (special section intro.). Hill, D., Jan.-Feb. 04, pp. 9-12.

Test equipment; cf., Automatic test equipment
Testing

book review; Digital Logic Testing and Simulation, 2nd edition (Miczo, A.; 2003). Davidson, S., Sept.-Oct. 04, pp. 448-449.

design & test education in Asia (Roundtable). July-Aug. 04, pp. 331-338.

functional verification and testbench generation (special section). Mar.-Apr. 04, pp. 80-143.

functional verification and testbench generation (special section intro.). Abadir, M.S., Mar.-Apr. 04, pp. 80-83.

industrial evaluation of DRAM tests. van de Goor, A.J., Sept.-Oct. 04, pp. 430-440.

protocol models to their implementation, a testing methodology. Varsamou, M., Sept.-Oct. 04, pp. 416-428.

testing at multi Gbps rates (special section). July-Aug. 04, pp. 274-321.

testing at multi Gbps rates (special section intro.). Ivanov, A., July-Aug. 04, pp. 274-276.

Testing; cf., Logic testing
Timing; cf., Timing circuits
Timing circuits

built-in parametric timing meas. unit. Ming-Jun Hsiao, July-Aug. 04, pp. 322-330.

megahertz, gigahertz, on-chip digital jitter meas. Sunter, S., July-Aug. 04, pp. 314-321.

Tree searching

safety property verification, seq. SAT and bounded model checking. Parthasarathy, G., Mar.-Apr. 04, pp. 132-143.

Very-large-scale integration

technol. closure of deep-submicron IC designs, integr. environ. Trevillyan, L., Jan.-Feb. 04, pp. 14-22.

Video signal processing

energy optim. for latency- and quality-constrained video applications. Chaeseok Im, Sept.-Oct. 04, pp. 358-366.

Video signals; cf., Video signal processing
VLSI

testing at multi Gbps rates (special section). July-Aug. 04, pp. 274-321.

testing at multi Gbps rates (special section intro.). Ivanov, A., July-Aug. 04, pp. 274-276.

Yield estimation

basics, back. Vandenberg, C., May-June 04, pp. 180

logic ccts., understanding yield losses. Appello, D., May-June 04, pp. 208-215.

manufacturability, logic synthesis. Nardi, A., May-June 04, pp. 192-199.

presence of massive nos. of defects, defect and error tolerance. Breuer, M.A., May-June 04, pp. 216-227.

SoC yield optim. via, embedded-memory test and fix infrastructure. Shoukourian, S., May-June 04, pp. 200-207.

very deep-submicron designs, revolutionizing mfg. procs. Magarshack, P., May-June 04, p. 181.