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Issue No.06 - November/December (2004 vol.21)
pp: 552-562
Fernanda Gusmao de Lima Kastensmidt , State University of Rio Grande do Sul
Gustavo Neuberger , Federal University of Rio Grande do Sul
Renato Fernandes Hentschke , Federal University of Rio Grande do Sul
Luigi Carro , Federal University of Rio Grande do Sul
Ricardo Reis , Federal University of Rio Grande do Sul
<it>Editors' note: </it>FPGAs have become prevalent in critical applications in which transient faults can seriously affect the circuit's operation. This article presents a fault tolerance technique for transient and permanent faults in SRAM-based FPGAs. This technique combines duplication with comparison (DWC) and concurrent error detection (CED) to provide a highly reliable circuit while maintaining hardware, pin, and power overheads far lower than with classic triple-modular-redundancy techniques. <it>—Dimitris Gizopoulos, University of Piraeus; and Yervant Zorian, Virage Logic</it>
Fernanda Gusmao de Lima Kastensmidt, Gustavo Neuberger, Renato Fernandes Hentschke, Luigi Carro, Ricardo Reis, "Designing Fault-Tolerant Techniques for SRAM-Based FPGAs", IEEE Design & Test of Computers, vol.21, no. 6, pp. 552-562, November/December 2004, doi:10.1109/MDT.2004.85
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