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Enhanced Equivalence Checking: Toward a Solidarity of Functional Verification and Manufacturing Test Generation
November/December 2004 (vol. 21 no. 6)
pp. 494-502
Jayanta Bhadra, Freescale Semiconductor
Narayanan Krishnamurthy, Freescale Semiconductor
Magdy S. Abadir, Freescale Semiconductor
Editor's note: This article, from the Motorola (now Freescale) PowerPC design group, presents an interesting synergy among test, equivalence verification, and constraints. The authors use RTL, gate, and switch models of a design in two different flows—one for test and one for functional verification—to show that rectifying constraints and merging tests between the two flows saves significant presilicon debug effort.
Citation:
Jayanta Bhadra, Narayanan Krishnamurthy, Magdy S. Abadir, "Enhanced Equivalence Checking: Toward a Solidarity of Functional Verification and Manufacturing Test Generation," IEEE Design & Test of Computers, vol. 21, no. 6, pp. 494-502, Nov.-Dec. 2004, doi:10.1109/MDT.2004.87
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