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TPartition: Testbench Partitioning for Hardware-Accelerated Functional Verification
November/December 2004 (vol. 21 no. 6)
pp. 484-493
Young-Il Kim, Korea Advanced Institute of Science and Technology
Chong-Min Kyung, Korea Advanced Institute of Science and Technology Integrated Circuit Design Education Center
Editor's note: This hybrid dynamic simulation scheme implements part of the simulator in software running on a processor and maps the rest onto a programmable hardware accelerator. An algorithm for hardware synthesis of behavioral testbenches enables better partitions, resulting in lower communication costs between the two components. —Sharad Malik, Princeton University
Citation:
Young-Il Kim, Chong-Min Kyung, "TPartition: Testbench Partitioning for Hardware-Accelerated Functional Verification," IEEE Design & Test of Computers, vol. 21, no. 6, pp. 484-493, Nov.-Dec. 2004, doi:10.1109/MDT.2004.101
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