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Issue No.06 - November/December (2004 vol.21)
pp: 472-482
Serdar Tasiran , Ko? University
Yuan Yu , Microsoft Research
ABSTRACT
<it>Editor's note: </it>This article uses simulation to bridge the gap between specification and formal verification of high-level models and simulation of RTL models. The authors apply their practical, two-phase procedure for defining the refinement map to the Alpha 21364 multiprocessing hardware. The methodology and tools they present can improve simulation coverage. —<it>Carl Pixley, Synopsys</it>
CITATION
Serdar Tasiran, Yuan Yu, Brannon Batson, "Linking Simulation with Formal Verification at a Higher Level", IEEE Design & Test of Computers, vol.21, no. 6, pp. 472-482, November/December 2004, doi:10.1109/MDT.2004.94
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