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| Rajesh Gupta, "Verification synergies," IEEE Design & Test of Computers, vol. 21, no. 6, pp. 457, November/December, 2004. | |||
| BibTex | x | ||
| @article{ 10.1109/MDT.2004.88, author = {Rajesh Gupta}, title = {Verification synergies}, journal ={IEEE Design & Test of Computers}, volume = {21}, number = {6}, issn = {0740-7475}, year = {2004}, pages = {457}, doi = {http://doi.ieeecomputersociety.org/10.1109/MDT.2004.88}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, } | |||
| RefWorks Procite/RefMan/Endnote | x | ||
| TY - MGZN JO - IEEE Design & Test of Computers TI - Verification synergies IS - 6 SN - 0740-7475 SP EP EPD - 457 A1 - Rajesh Gupta, PY - 2004 VL - 21 JA - IEEE Design & Test of Computers ER - | |||
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/MDT.2004.88
Citation:
Rajesh Gupta, "Verification synergies," IEEE Design & Test of Computers, vol. 21, no. 6, pp. 457, Nov.-Dec. 2004, doi:10.1109/MDT.2004.88
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