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Issue No.05 - September/October (2004 vol.21)
pp: 450-451
Published by the IEEE Computer Society
Erich Marschner , Cadence
The role of standards in EDA has evolved through the years, and it continues to evolve as the industry matures. Understanding how the role of EDA standards has changed over time can help us see where standards will be going in the future.
The role of standards in EDA has evolved through the years, and it continues to evolve as the industry matures. Understanding how the role of EDA standards has changed over time can help us see where standards will be going in the future.
The EDA industry has existed for only about 25 years. In the early 1980s, there were no standards; or, rather, there were only ad hoc standards—from the technology of Daisy, Mentor, and Valid, the big-three EDA companies at the time. As more and more companies began offering tools, each with its own input language, users ran into interoperability issues and issues of obsolescence—design data became useless if the tool it was written for was no longer available. In response, the US Department of Defense (DoD) sponsored the development of a standard hardware design language, VHDL, which became the first IEEE standard for EDA (VHDL 1076-1987). In parallel, Verilog was growing in popularity, and it became an IEEE standard in 1993 (Verilog 1364-1993).
Standards have always benefited users, and EDA standards are no exception. However, in the late 1980s, most EDA vendors viewed standards with some degree of suspicion and trepidation. Many believed that standardization meant lack of differentiation, and that standardizing design languages would quickly lead to commoditizing the tools that those languages drive. In those early years, many vendors also argued that standardization would stifle innovation. To some degree, they may have been right—simulators have certainly become commoditized during the past decade. At the same time, standard hardware description languages (HDLs) provided fertile ground for the growth of synthesis technology, which delivered a huge productivity increase in chip design.
In the 1990s, the existing two IEEE standard RTL design languages (VHDL and Verilog) and various other standards such as the Electronic Design Interchange Format (EDIF) led one commentator to note, "the nice thing about standards is that there are so many to choose from." The not-so-nice thing about having multiple standards was that it led to "standards wars" between organizations trying to prove that one language or another was the best language for design. If anything stifled innovation during the 1990s, the competition between the VHDL and Verilog camps was probably to blame. Even so, both standards evolved further during that time, largely by borrowing from each other: VHDL developed the VHDL Initiative Towards ASIC Libraries (Vital, or IEEE 1076.4) to define a Verilog-like standard bit type and operations; Verilog, in turn, added new operators borrowed from VHDL. But most importantly, EDA vendors began to recognize the competitive advantage of supporting standards during this period.
As the VHDL-Verilog standards war wound down, the energy that had been committed to competition needed a new outlet. The war officially ended when the marketing organizations for VHDL and Verilog—VHDL International (VI) and Open Verilog International (OVI)—merged to form Accellera, an organization dedicated to accelerating the development of EDA standards. Previous IEEE standards were based on existing technology (VHDL 1076 on the DoD-sponsored VHDL development effort, and Verilog 1364 on the original Gateway-Cadence Verilog-XL language), but Accellera took this process a step further by actively soliciting proprietary technology donations to serve as the basis for a standard. Leveraging EDA vendors' newfound appreciation for the competitive value of being the first to implement a standard, this approach has led to more rapid evolution of Verilog (in the form of SystemVerilog) and to new standards in other areas, such as Accellera's Property Specification Language (PSL). At the same time, it has raised concerns for ensuring that companies develop standards fairly, so that no one company or block of companies can control the standard definition to serve their own proprietary interests.
This issue is an element of recent decisions made in various IEEE working groups. Historically, most EDA standards have developed under the aegis of the Design Automation Standards Committee (DASC), where working groups consist of individual IEEE members, and each individual has a single vote. In contrast, some other standards have developed under the aegis of the Corporate Advisory Group (CAG), where working groups consist of corporate representatives, and each corporation has a single vote. Accellera has a similar structure in which only certain classes of Accellera corporate members are allowed to vote on standards. The question is, Which structure—individual or corporate entity voting—leads to a more fair decision-making process for standards development? Or, perhaps the question should be, Is fairness the correct metric, or should the higher good of market relevance prevail?
The new SystemVerilog working group for IEEE P1800, cosponsored by the DASC and the CAG, has elected to adopt corporate voting. In contrast, the DASC-sponsored VHDL 1076-200x working group has just voted almost unanimously to reject corporate entity voting and continue with individual voting. Critics of individual voting argue that the individual voting approach used in DASC working groups has led to companies trying to dominate the voting by "packing" a committee with its individual representatives, whereas the corporate entity voting approach used in CAG working groups is not subject to the same manipulation. Other critics argue that corporate entity voting tends to make standards developments more of a proprietary battleground, and that it effectively disenfranchises the individuals who provide the technical expertise required to create a standard.
In any case, the focus of the discussion is already moving from fairness to funding: Which approach is more likely to garner enough interest and support to cover the cost of developing a new standard? Will corporate entity voting encourage corporations to join the CAG, and also to donate funds to the working group to pay for technical editing, technical consultants, and meeting infrastructure? Or will standards development based on volunteer efforts of individuals (each with a vote) remain economically viable? At this point, these questions remain unanswered.
One thing history shows is that standards and standards development are never boring. In fact, the nice thing about standards (and standards development processes) is that they keep changing to address new problems and new issues, both technological and political. As observers of this process, we look forward to reporting on the relative success of each of these approaches and discovering which is seen to best suit the needs of an evolving industry.
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