Issue No.05 - September/October (2004 vol.21)
Ad J. van de Goor , Delft University of Technology
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/MDT.2004.51
This application of 40 well-known memory tests to 1,896 1-Mbyte X 4 DRAM chips, used up to 48 different stress combinations with each test. The results show the importance of selecting the right stress combination, and that the theoretically better tests' those covering more different functional faults' also have higher fault coverage.
Ad J. van de Goor, "An Industrial Evaluation of DRAM Tests", IEEE Design & Test of Computers, vol.21, no. 5, pp. 430-440, September/October 2004, doi:10.1109/MDT.2004.51