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Evaluating Schedulers for Multimedia Processing on Buffer-Constrained SoC Platforms
September/October 2004 (vol. 21 no. 5)
pp. 368-377
Alexander Maxiaguine, Swiss Federal Institute of Technology
Samarjit Chakraborty, National University of Singapore
Simon K?, Swiss Federal Institute of Technology
Lothar Thiele, Swiss Federal Institute of Technology
Editors' note:Scheduling on-chip resources using analytical techniques is becoming increasingly important in multimedia processing. This article presents an analytical framework for designing and evaluating schedulers for SoC multimedia platforms. The modeling technique subsumes standard event models used in real-time scheduling and accurately captures the variability in task execution requirements.
--Radu Marculescu, Carnegie Mellon University; and Petru Eles, Linköping University
Citation:
Alexander Maxiaguine, Samarjit Chakraborty, Simon K?, Lothar Thiele, "Evaluating Schedulers for Multimedia Processing on Buffer-Constrained SoC Platforms," IEEE Design & Test of Computers, vol. 21, no. 5, pp. 368-377, Sept.-Oct. 2004, doi:10.1109/MDT.2004.60
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