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A Built-In Parametric Timing Measurement Unit
July/August 2004 (vol. 21 no. 4)
pp. 322-330
| ASCII Text | x | ||
| Ming-Jun Hsiao, Jing-Reng Huang, Tsin-Yuan Chang, "A Built-In Parametric Timing Measurement Unit," IEEE Design & Test of Computers, vol. 21, no. 4, pp. 322-330, July/August, 2004. | |||
| BibTex | x | ||
| @article{ 10.1109/MDT.2004.22, author = {Ming-Jun Hsiao and Jing-Reng Huang and Tsin-Yuan Chang}, title = {A Built-In Parametric Timing Measurement Unit}, journal ={IEEE Design & Test of Computers}, volume = {21}, number = {4}, issn = {0740-7475}, year = {2004}, pages = {322-330}, doi = {http://doi.ieeecomputersociety.org/10.1109/MDT.2004.22}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, } | |||
| RefWorks Procite/RefMan/Endnote | x | ||
| TY - MGZN JO - IEEE Design & Test of Computers TI - A Built-In Parametric Timing Measurement Unit IS - 4 SN - 0740-7475 SP322 EP330 EPD - 322-330 A1 - Ming-Jun Hsiao, A1 - Jing-Reng Huang, A1 - Tsin-Yuan Chang, PY - 2004 VL - 21 JA - IEEE Design & Test of Computers ER - | |||
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/MDT.2004.22
On-chip timing-measurement units are needed because accessibility to internal nodes in SoCs is very limited, and performing time interval measurements using automatic test equipment is very difficult and expensive. This article presents a parametric timing measurement solution, which uses self-timed techniques and delivers high linearity and improved accuracy, at low risk of measurement error.
Citation:
Ming-Jun Hsiao, Jing-Reng Huang, Tsin-Yuan Chang, "A Built-In Parametric Timing Measurement Unit," IEEE Design & Test of Computers, vol. 21, no. 4, pp. 322-330, July-Aug. 2004, doi:10.1109/MDT.2004.22
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