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Issue No.03 - May/June (2004 vol.21)
pp: 248-258
Bhaskar Chatterjee , University of Waterloo
Manoj Sachdev , University of Waterloo
Ali Keshavarzi , Intel Laboratories
ABSTRACT
Timing-only parametric defects are a major source of failures and test escapes in modern ICs. A DFT technique using compound domino logic gates with footer transistors uncovers these hard-to-detect defects with minimal performance and power overheads.
CITATION
Bhaskar Chatterjee, Manoj Sachdev, Ali Keshavarzi, "DFT for Delay Fault Testing of High-Performance Digital Circuits", IEEE Design & Test of Computers, vol.21, no. 3, pp. 248-258, May/June 2004, doi:10.1109/MDT.2004.10
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