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New Challenges in Delay Testing of Nanometer, Multigigahertz Designs
May/June 2004 (vol. 21 no. 3)
pp. 241-247
T.M. Mak, Intel
Angela Krstic, University of California, Santa Barbara
Kwang-Ting (Tim) Cheng, University of California, Santa Barbara
Li-C. Wang, University of California, Santa Barbara
Less predictable path delays and many paths with delays close to the clock period are the main trends affecting the delay testability of deep-submicron designs. This article examines the challenges in meeting the quality requirements of gigascale integration, and explores functional testing as well as statistical models and methods that could alleviate some of those problems.
Citation:
T.M. Mak, Angela Krstic, Kwang-Ting (Tim) Cheng, Li-C. Wang, "New Challenges in Delay Testing of Nanometer, Multigigahertz Designs," IEEE Design & Test of Computers, vol. 21, no. 3, pp. 241-247, May-June 2004, doi:10.1109/MDT.2004.17
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