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New Challenges in Delay Testing of Nanometer, Multigigahertz Designs
May/June 2004 (vol. 21 no. 3)
pp. 241-247
ASCII Text
x 
 
T.M. Mak, Angela Krstic, Kwang-Ting (Tim) Cheng, Li-C. Wang, "New Challenges in Delay Testing of Nanometer, Multigigahertz Designs," IEEE Design & Test of Computers, vol. 21, no. 3, pp. 241-247, May/June, 2004.
 
 
BibTex
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@article{ 10.1109/MDT.2004.17,
author = {T.M. Mak and Angela Krstic and Kwang-Ting (Tim) Cheng and Li-C. Wang},
title = {New Challenges in Delay Testing of Nanometer, Multigigahertz Designs},
journal ={IEEE Design & Test of Computers},
volume = {21},
number = {3},
issn = {0740-7475},
year = {2004},
pages = {241-247},
doi = {http://doi.ieeecomputersociety.org/10.1109/MDT.2004.17},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - MGZN
JO - IEEE Design & Test of Computers
TI - New Challenges in Delay Testing of Nanometer, Multigigahertz Designs
IS - 3
SN - 0740-7475
SP241
EP247
EPD - 241-247
A1 - T.M. Mak,
A1 - Angela Krstic,
A1 - Kwang-Ting (Tim) Cheng,
A1 - Li-C. Wang,
PY - 2004
VL - 21
JA - IEEE Design & Test of Computers
ER -
 
T.M. Mak, Intel
Angela Krstic, University of California, Santa Barbara
Kwang-Ting (Tim) Cheng, University of California, Santa Barbara
Li-C. Wang, University of California, Santa Barbara
Less predictable path delays and many paths with delays close to the clock period are the main trends affecting the delay testability of deep-submicron designs. This article examines the challenges in meeting the quality requirements of gigascale integration, and explores functional testing as well as statistical models and methods that could alleviate some of those problems.
Citation:
T.M. Mak, Angela Krstic, Kwang-Ting (Tim) Cheng, Li-C. Wang, "New Challenges in Delay Testing of Nanometer, Multigigahertz Designs," IEEE Design & Test of Computers, vol. 21, no. 3, pp. 241-247, May-June 2004, doi:10.1109/MDT.2004.17
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