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Defect and Error Tolerance in the Presence of Massive Numbers of Defects
May/June 2004 (vol. 21 no. 3)
pp. 216-227
Melvin A. Breuer, University of Southern California
Sandeep K. Gupta, University of Southern California
T.M. Mak, Intel
As scaling approaches the physical limits of devices, we will continue to see increasing levels of process variations, noise, and defect densities. Many applications today can tolerate certain levels of errors resulting from such factors. This article introduces a new approach for error tolerance resulting in chips containing only errors acceptable for such applications.
Citation:
Melvin A. Breuer, Sandeep K. Gupta, T.M. Mak, "Defect and Error Tolerance in the Presence of Massive Numbers of Defects," IEEE Design & Test of Computers, vol. 21, no. 3, pp. 216-227, May-June 2004, doi:10.1109/MDT.2004.8
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