Issue No.03 - May/June (2004 vol.21)
Alessandra Nardi , University of California, Berkeley
Alberto L. Sangiovanni-Vincentelli , University of California, Berkeley
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/MDT.2004.15
Typically, design optimization during synthesis is for area and/or performance, while optimization for yield occurs at the layout level. To obtain more effective yield improvement, this article proposes elevating the abstraction level for yield optimization by introducing an interesting approach to yield-driven logic synthesis.
Alessandra Nardi, Alberto L. Sangiovanni-Vincentelli, "Logic Synthesis for Manufacturability", IEEE Design & Test of Computers, vol.21, no. 3, pp. 192-199, May/June 2004, doi:10.1109/MDT.2004.15