• Variation in etching rate can cause residual-induced failures, which create smaller vias with higher resistance. Over time, this can turn into a permanent open fault.
• Variation in etching rate can also result in residuals on interconnects, which can cause an intermittent contact. This situation might eventually turn into a permanent short.
• A similar variation in layer thickness can cause electromigration in metallic or dielectric layers. This results in a higher resistance that manifests as intermittent delays. Over time, the high-resistance in interconnects can become permanent opens.
• The variation in layer thickness can also result in adjacent or crossing conductor signals, which cause intermittent contacts. This can, over time, turn into permanent shorts.
Yervant Zorian is vice president and chief scientist of Virage Logic. He previously was the chief technology advisor of LogicVision and a Distinguished Member of Technical Staff at Bell Labs. Zorian has an MSc in computer engineering from the University of Southern California, a PhD in electrical engineering from McGill University, and an executive MBA from Wharton School of Business, University of Pennsylvania. He is the IEEE Computer Society vice president for technical activities, and a Fellow of the IEEE.
Dimitris Gizopoulos is an assistant professor in the Department of Informatics at the University of Piraeus, Greece. His research interests include self-testing of embedded processors; SoC and online testing; and yield and reliability improvement. Gizopoulos has a PhD in computer science from the University of Athens, Greece. He is the Tutorials and Education Group Chair of the Test Technology Technical Council, a Senior member of the IEEE, and a Golden Core member of the IEEE Computer Society.