This Article 
   
 Share 
   
 Bibliographic References 
   
 Add to: 
 
Digg
Furl
Spurl
Blink
Simpy
Google
Del.icio.us
Y!MyWeb
 
 Search 
   
A Top-Down Methodology for Microprocessor Validation
March/April 2004 (vol. 21 no. 2)
pp. 122-131
Prabhat Mishra, University of California, Irvine
Nikil Dutt, University of California, Irvine
Magdy S. Abadir, Motorola
A major challenge in today's functional verification is the lack of a formal specification with which to compare the RTL model. The authors propose a novel top-down verification approach that allows specification of a design above the RTL. From this specification, it is possible to automatically generate assertion models and RTL reference models. The authors also demonstrate that symbolic simulation and equivalence checking can be applied to verify an RTL design against its specification.
Citation:
Prabhat Mishra, Nikil Dutt, Narayanan Krishnamurthy, Magdy S. Abadir, "A Top-Down Methodology for Microprocessor Validation," IEEE Design & Test of Computers, vol. 21, no. 2, pp. 122-131, March-April 2004, doi:10.1109/MDT.2004.1277905
Usage of this product signifies your acceptance of the Terms of Use.