• a model describing the target architecture, and
• a generic constraint-solving engine for test generation.
• a test generator to emulate all possible inputs from the surrounding units,
• a golden model to predict the unit's behavior, and
• a monitor program to check for possible errors.
Magdy S. Abadir manages the High Performance Tools and Methodology Group at Motorola's PowerPC Design Center in Austin, Texas. He is also an adjunct faculty member of the Computer Engineering Department at the University of Texas at Austin. His research interests include microprocessor test and verification, test economics, EDA tools, and DFT. Abadir has a BS in computer science from the University of Alexandria, Egypt; an MS in computer science from the University of Saskatchewan, Saskatoon, Canada; and a PhD in electrical engineering from the University of Southern California. He has cofounded and chaired a series of international workshops on the economics of design, test, and manufacturing; and on microprocessor test and verification. A coeditor of several books on those subjects, Abadir has published more than 120 conference and technical papers on test economics, DFT, computer-aided design, high-level test generation, and design verification and economics. He is a senior member of the IEEE.
Li-C. Wang is an assistant professor in the Department of Electrical and Computer Engineering at the University of California, Santa Barbara. His research interests include microprocessor test and verification, defect-oriented testing, ATPG SAT solver development, and statistical methods for speed test and validation. Wang has a BS in computer engineering from National Chiao Tung University, Taiwan, and an MS in computer science and a PhD in electrical and computer engineering, both from the University of Texas at Austin. He received best-paper awards from the 1998 Design Automation and Test in Europe (DATE) Conference, the 1999 IEEE VLSI Test Symposium, and DATE 2003 for his work on PowerPC verification, commercial experiments on novel ATPG methods, and delay defect diagnosis, respectively. He is cofounder and program chair of the IEEE Microprocessor Test and Verification (MTV) Workshop and is a member of the IEEE.