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Issue No.01 - January/February (2004 vol.21)
pp: 56-63
Kaushik Roy , Purdue University
ABSTRACT
<p>Two CMOS design techniques use dual threshold voltages to reduce power consumption while maintaining high performance. Simulation results show power savings of 21% for one technique at low activity, and for the other, 19% at high activity and 38% at low activity.</p>
CITATION
Naran Sirisantana, Kaushik Roy, "Low-Power Design Using Multiple Channel Lengths and Oxide Thicknesses", IEEE Design & Test of Computers, vol.21, no. 1, pp. 56-63, January/February 2004, doi:10.1109/MDT.2004.1261850
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