2003 Annual Index Volume 20
NOVEMBER/DECEMBER 2003 (Vol. 20, No. 6) pp. 108-119
0740-7475/03/$31.00 © 2003 IEEE

Published by the IEEE Computer Society
2003 Annual Index IEEE Design & Test of Computers Volume 20
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This index includes all items appearing in this periodical during 2003 that are considered to have archival value. (The item title is listed only under the primary author entry in the author index.)

Author Index

A

Al-Hashimi, B.M., see Nicolici, N., July-Aug. 03, pp. 48-55.

Anand, D., , B. Cowan, O. Farnsworth, P. Jakobsen, S. Oakland, M.R. Ouellette, and D.L. Wheater, "An On-Chip Self-Repair Calculation and Fusing Methodology," Sept.-Oct. 03, pp. 67-75.

Ashenden, P.J., "Boundary Scan Test Standards," Jan.-Feb. 03, pp. 91-92.

Ashenden, P.J., "VHDL-200X: The Next Revision," Standards, May-June 03, pp. 112-113.

Auvergne, D., see Daga, J.M., Jan.-Feb. 03, pp. 68-75.

Ayers, D., see Grochowski, E., May-June 03, pp. 40-47.

Azais, F., Y. Bertrand, M. Renovell, A. Ivanov, and S. Tabatabaei, "An All-Digital DFT Scheme for Testing Catastrophic Faults in PLLs," Jan.-Feb. 03, pp. 60-67.

Azais, F., see Kac, U., Mar.-Apr. 03, pp. 32-39.

B

Bandapati, S.K., S.C. Smith, and M. Choi, "Design and Characterization of Null Convention Self-Time Multipliers, "Nov.-Dec. 03, pp. 26-36.

Barnhart, C.F., see Eklow, B., Sept.-Oct. 03, pp. 76-83.

Bennetts, R.G., see Lobetti-Bodoni, M., Mar.-Apr. 03, pp. 5-7.

Bennetts, R.G., see Marinissen, E.J., Mar.-Apr. 03, pp. 8-18.

Benso, A., S. Di Carlo, G. Di Natale, and P. Prinetto, "Online Self-Repair of FIR Filters," May-June 03, pp. 50-57.

Benso, A., S. Di Carlo, P. Prinetto, and Y. Dorian, "A Hierarchical Infrastructure for Sock Test Management," July-Aug. 03, pp. 32-39.

Benware, B.R., see Madge, R., Sept.-Oct. 03, pp. 46-53.

Bertrand, Y., see Azais, F., Jan.-Feb. 03, pp. 60-67.

Blaauw, D., see Panda, R., May-June 03, pp. 16-22.

Bruels, N., see Raab, W., Jan.-Feb. 03, pp. 8-15.

Butler, K.M., K.-T. Cheng, and L.-C. Wang, "Guest Editors' Introduction: Speed Test and Speed Binning for Complex ICs," Sept.-Oct. 03, pp. 6-7.

C

Cardoso, J.M.P., and H.C. Neto, "Compilation for FPGA-Based Reconfigurable Hardware," Mar.-Apr. 03, pp. 65-75.

Carro, L., M. Negreiros, G.P. Jahn, A.A. de Souza, Jr., and D.T. Franco, "Circuit-Level Considerations for Mixed-Signal Programmable Components," Jan.-Feb. 03, pp. 76-84.

Catthoor, F., see Cupak, M., Mar.-Apr. 03, pp. 56-64.

Cheng, K.-T., see Butler, K.M., Sept.-Oct. 03, pp. 6-7.

Chen I-Ling, see Chien-Nan Jimmy Liu, Mar.-Apr. 03, pp. 48-55.

Chien-Nan Jimmy Liu, I-Ling Chen, and Jing-Yang Jou, "A Design-for-Verification Technique for Functional Pattern Reduction," Mar.-Apr. 03, pp. 48-55.

Choi, M., see Bandapati, S.K., Nov.-Dec. 03, pp. 26-36.

Choi Kiyoung, see Jong-eun Lee, Jan.-Feb. 03, pp. 26-33.

Clark, C., and M. Ricchetti, "Infrastructure IP for Configuration and Test of Boards and Systems," May-June 03, pp. 78-87.

Cory, B.D., R. Kapur, and B. Underwood, "Speed Binning with Path Delay Test in 150-nm Technology," Sept.-Oct. 03, pp. 41-45.

Cowan, B., see Anand, D., Sept.-Oct. 03, pp. 67-75.

Crouch, A.L., J.C. Potter, and J. Doege, "AC Scan Path Selection for Physical Debugging," Sept.-Oct. 03, pp. 34-40.

Cupak, M., F. Catthoor, and H.J. De Man, "Efficient System-Level Functional Verification Methodology for Multimedia Applications," Mar.-Apr. 03, pp. 56-64.

D

Daasch, W.R., see Madge, R., Sept.-Oct. 03, pp. 46-53.

Daga, J.M., C. Papaix, M. Merandat, S. Ricard, G. Medulla, J. Guichaoua, and D. Auvergne, "Design Techniques for EEPROMs Embedded in Portable Systems on Chips," Jan.-Feb. 03, pp. 68-75.

De Man, H.J., see Cupak, M., Mar.-Apr. 03, pp. 56-64.

de Souza, A.A., Jr., see Carro, L., Jan.-Feb. 03, pp. 76-84.

Di Carlo, S., see Benso, A., May-June 03, pp. 50-57.

Di Carlo, S., see Benso, A., July-Aug. 03, pp. 32-39.

Di Natale, G., see Benso, A., May-June 03, pp. 50-57.

Doege, J., see Crouch, A.L., Sept.-Oct. 03, pp. 34-40.

Dutt, N.D., see Jong-eun Lee, Jan.-Feb. 03, pp. 26-33.

E

Eklow, B., C.F. Barnhart, and K.P. Parker, "IEEE 1149.6: A Boundary Scan Standard for Advanced Digital Networks," Sept.-Oct. 03, pp. 76-83.

Engin, N., and H.G. Kerkhoff, "Fast Fault Simulation for Nonlinear Analog Circuits, " Mar.-Apr. 03, pp. 40-47.

F

Farnsworth, O., see Anand, D., Sept.-Oct. 03, pp. 67-75.

Franco, D.T., see Carro, L., Jan.-Feb. 03, pp. 76-84.

G

Gopalakrishnan, G., see Hosabettu, R., July-Aug. 03, pp. 4-14.

Grochowski, E., D. Ayers, and V. Tiwari, "Microarchitectural dl/dt Control," May-June 03, pp. 40-47.

Guerra e Silva, L., see Marques-Silva, J., July-Aug. 03, pp. 16-21.

Guichaoua, J., see Daga, J.M., Jan.-Feb. 03, pp. 68-75.

Gupta, S.K., see Quasem, M.S., May-June 03, pp. 68-77.

H

Hachmann, U., see Raab, W., Jan.-Feb. 03, pp. 8-15.

Harnisch, J., see Raab, W., Jan.-Feb. 03, pp. 8-15.

Harris, I.G., "Fault Models and Test Generation for Hardware-Software Covalidation," July-Aug. 03, pp. 40-47.

Hassoun, S., Yong-Bin Kim, and Fabrizio Lombardi, "Guest Editors' Introduction: Clockless VLSI Systems," Nov.-Dec. 03, pp. 5-8.

Hassoun, S. see Nassif, S.R., May-June 03, pp. 5-6.

Hohenauer, M., see Wahlen, O., Jan.-Feb. 03, pp. 34-41.

Hollmann, H., see Marinissen, E.J., Mar.-Apr. 03, pp. 8-18.

Hosabettu, R., G. Gopalakrishnan, and M. Srivas, "A Practical Methodology for Verifying Pipelined Microarchitectures," July-Aug. 03, pp. 4-14.

I

I-Ling Chen, see Chien-Nan Jimmy Liu, Mar.-Apr. 03, pp. 48-55.

Ivanov, A., see Azais, F., Jan.-Feb. 03, pp. 60-67.

J

Jahn, G.P., see Carro, L., Jan.-Feb. 03, pp. 76-84.

Jakobsen, P., see Anand, D., Sept.-Oct. 03, pp. 67-75.

Jiang Zhigang, see Quasem, M.S., May-June 03, pp. 68-77.

Jimmy Liu Chien-Nan, see Chien-Nan Jimmy Liu, Mar.-Apr. 03, pp. 48-55.

Jing-Yang Jou, see Chien-Nan Jimmy Liu, Mar.-Apr. 03, pp. 48-55.

Jin Kim Woo, see Woo Jin Kim, Nov.-Dec. 03, pp. 52-59.

Jong-eun Lee, Kiyoung Choi, and N.D. Dutt, "Compilation Approach for Coarse-Grained Reconfigurable Architectures," Jan.-Feb. 03, pp. 26-33.

Jou Jing-Yang, see Chien-Nan Jimmy Liu, Mar.-Apr. 03, pp. 48-55.

K

Kac, U., F. Novak, F. Azais, P. Nouet, and M. Renovell, "Extending IEEE Std. 1149.4 Analog Boundary Modules to Enhance Mixed-Signal Test," Mar.-Apr. 03, pp. 32-39.

Kahng, A.B., "Error Tolerance," The Road Ahead,Jan.-Feb. 03, pp. 86-87.

Kahng, A.B., "Bringing Down NRE," The Road Ahead,May-June 03, pp. 110-111.

Kapur, R., see Cory, B.D., Sept.-Oct. 03, pp. 41-45.

Kassab, M., see Rajski, J., Sept.-Oct. 03, pp. 58-66.

Kerkhoff, H.G., see Engin, N., Mar.-Apr. 03, pp. 40-47.

Kim, K.S., S. Mitra, and P.G. Ryan, "Delay Defect Characteristics and Testing Strategies," Sept.-Oct. 03, pp. 8-16.

Kim Woo Jin, see Woo Jin Kim, Nov.-Dec. 03, pp. 51-58.

Kim Yong-Bin, see Woo Jin Kim, Nov.-Dec. 03, pp. 51-58.

Kiyoung Choi, see Jong-eun Lee, Jan.-Feb. 03, pp. 26-33.

Kratiter, B., see Zheng, H., May-June 03, pp. 24-31.

L

Lee Jong-eun, see Jong-eun Lee, Jan.-Feb. 03, pp. 26-33.

Leupers, R., see Wahlen, O., Jan.-Feb. 03, pp. 34-41.

Liljeberg, P., see Plosila, J., Nov.-Dec. 03, pp. 44-50.

Lin, X., R. Press, J. Rajski, P. Reuter, T. Rinderknecht, B. Swanson, and N. Tamarapalli, "High-Frequency, At-Speed Scan Testing," Sept.-Oct. 03, pp. 17-25.

Liu Chien-Nan Jimmy, see Chien-Nan Jimmy Liu, Mar.-Apr. 03, pp. 48-55.

Lobetti-Bodoni, M., and R.G. Bennetts, "Guest Editors' Introduction: Board Test," Mar.-Apr. 03, pp. 5-7.

M

Madge, R., B.R. Benware, and W.R. Daasch, "Obtaining High Defect Coverage for Frequency-Dependent Defects in Complex ASICs," Sept.-Oct. 03, pp. 46-53.

Marek-Sadowska, M., see Mukheijee, A., May-June 03, pp. 32-39.

Marinissen, E.J., B. Vermeulen, H. Hollmann, and R.G. Bennetts, "Minimizing Pattern Count for Interconnect Test under a Ground Bounce Constraint," Mar.-Apr. 03, pp. 8-18.

Marques-Silva, J., and L. Guerra e Silva, "Solving Satisfiability in Combinational Circuits," July-Aug. 03, pp. 16-21.

Martin, A.J., M. Nystroom, and C.G. Wong, "Three Generations of Asynchronous Microprocessors," Nov.-Dec. 03, pp. 9-17.

Masteller, S., "Cycle Decomposition in NCLTM," Nov..-Dec. 03, pp. 38-43.

Maxwell, P.C., "Wafer-Package Test Mix for Optimal Defect Detection and Test Time Savings," Sept.-Oct. 03, pp. 84-89.

Medulla, G., see Daga, J.M., Jan.-Feb. 03, pp. 68-75.

Merandat, M., see Daga, J.M., Jan.-Feb. 03, pp. 68-75.

Meyr, H., see Wahlen, O., Jan.-Feb. 03, pp. 34-41.

Miranda, J.M., see Van Treuren, B.G., Mar.-Apr. 03, pp. 20-25.

Mitra, S., see Kim, K.S., Sept.-Oct. 03, pp. 8-16.

Mrugalski, G., J. Tyszer, and J. Rajski, "2D Test Sequence Generators," Jan.-Feb. 03, pp. 51-59.

Mukheijee, A., and M. Marek-Sadowska, "Clock and Power Gating with Timing Closure," May-June 03, pp. 32-39.

Mukherjee, N., see Rajski, J., Sept.-Oct. 03, pp. 58-66.

N

Nassif, S.R., and S. Hassoun, "Guest Editors' Introduction: On-Chip Power Distribution Networks," May-June 03, pp. 5-6.

Negreiros, M., see Carro, L., Jan.-Feb. 03, pp. 76-84.

Neto, H.C., see Cardoso, J.M.P., Mar.-Apr. 03, pp. 65-75.

Nicolici, N., and B.M. Al-Hashimi, "Power-Conscious Test Synthesis and Scheduling," July-Aug. 03, pp. 48-55.

Nouet, P., see Kac, U., Mar.-Apr. 03, pp. 32-39.

Novak, F., see Kac, U., Mar.-Apr. 03, pp. 32-39.

Nystroom, M., see Martin, A.J., Nov.-Dec. 03, pp. 9-17.

O

Oakland, S., see Anand, D., Sept.-Oct. 03, pp. 67-75.

Orailoglu, A., and A. Veidenbaum, "Guest Editors' Introduction: Application-Specific Microprocessors," Jan.-Feb. 03, pp. 6-7.

Orailoglu, A., see Petrov, P., Jan.-Feb. 03, pp. 18-25.

Orailoglu, A., see Sinanoglu, O., July-Aug. 03, pp. 22-30.

Ouellette, M.R., see Anand, D., Sept.-Oct. 03, pp. 67-75.

P

Panda, R., S. Sundareswaran, and D. Blaauw, "Impact of Low-Impedance Substrate on Power Supply Integrity," May-June 03, pp. 16-22.

Papaix, C., see Daga, J.M., Jan.-Feb. 03, pp. 68-75.

Parker, K.P., see Eklow, B., Sept.-Oct. 03, pp. 76-83.

Pateras, S., "Achieving At-Speed Structural Test," Sept.-Oct. 03, pp. 26-33.

Petrov, P., and A. Orailoglu, "Application-Specific Instruction Memory Customizations for Power-Efficient Embedded Processors," Jan.-Feb. 03, pp. 18-25.

Pileggi, L., see Zheng, H., May-June 03, pp. 24-31.

Plosila, J., T. Seceleanu, and P. Liljeberg, "Implementation of a Self-Timed Segmented Bus," Nov..-Dec. 03, pp. 44-50.

Pnevinatikatos, D.N., L. Sourdis, and K. Vlachos, "An Efficient, Low-Cost I/O Subsystem for Network Processors," July-Aug. 03, pp. 56-64.

Potter, J.C., see Crouch, A.L., Sept.-Oct. 03, pp. 34-40.

Press, R., see Lin, X., Sept.-Oct. 03, pp. 17-25.

Prinetto, P., see Benso, A., May-June 03, pp. 50-57.

Prinetto, P., see Benso, A., July-Aug. 03, pp. 32-39.

Q

Qian, J., see Rajski, J., Sept.-Oct. 03, pp. 58-66.

Quasem, M.S., Zhigang Jiang, and S.K. Gupta, "Benefits of a SoC-Specific Test Methodology," May-June 03, pp. 68-77.

R

Raab, W., N. Bruels, U. Hachmann, J. Harnisch, U. Ramacher, C. Sauer, and A. Techmer, "A 100-GOPS Programmable Processor for Vehicle Vision Systems," Jan.-Feb. 03, pp. 8-15.

Rajski, J., see Mrugalski, G., Jan.-Feb. 03, pp. 51-59.

Rajski, J., see Lin, X., Sept.-Oct. 03, pp. 17-25.

Rajski, J., M. Kassab, N. Mukherjee, N. Tamarapalli, J. Tyszer, and J. Qian, "Embedded Deterministic Test for Low-Cost Manufacturing," Sept.-Oct. 03, pp. 58-66.

Ramacher, U., see Raab, W., Jan.-Feb. 03, pp. 8-15.

Renovell, M., see Azais, F., Jan.-Feb. 03, pp. 60-67.

Renovell, M., see Kac, U., Mar.-Apr. 03, pp. 32-39.

Reuter, P., see Lin, X., Sept.-Oct. 03, pp. 17-25.

Ricard, S., see Daga, J.M., Jan.-Feb. 03, pp. 68-75.

Ricchetti, M., see Clark, C., May-June 03, pp. 78-87.

Rich, D.I., "The Evolution of SystemVerilog," Standards,July-Aug. 03, pp. 82-84.

Rinderknecht, T., see Lin, X., Sept.-Oct. 03, pp. 17-25.

Ryan, P.G., see Kim, K.S., Sept.-Oct. 03, pp. 8-16.

S

Salamati, M., and D. Stranneby, "Electromagnetic Signatures as a Tool for Connectionless Test," Mar.-Apr. 03, pp. 26-30.

Sangiovanni-Vincentelli, A., "The Tides of EDA," Nov.-Dec. 03, pp. 59-75.

Sapatnekar, S.S. and H. Su, "Analysis and Optimization of Power Grids," May-June 03, pp. 7-15.

Sauer, C., see Raab, W., Jan.-Feb. 03, pp. 8-15.

Seceleanu, T., see Plosila, J., Nov.-Dec. 03, pp. 44-50.

Shoukourian, S., see Zorian, Y., May-June 03, pp. 58-66.

Sinanoglu, O., and A. Orailoglu, "Compacting Test Responses for Deeply Embedded SoC Cores," July-Aug. 03, pp. 22-30.

Smith, S.C., see Bandapati, S.K., Nov.-Dec. 03, pp. 26-36.

Sourdis, L., see Pnevinatikatos, D.N., July-Aug. 03, pp. 56-64.

Srivas, M., see Hosabettu, R., July-Aug. 03, pp. 4-14.

Stranneby, D., see Salamati, M., Mar.-Apr. 03, pp. 26-30.

Su, H., see Sapatnekar, S.S., May-June 03, pp. 7-15.

Sundareswaran, S., see Panda, R., May-June 03, pp. 16-22.

Swanson, B., see Lin, X., Sept.-Oct. 03, pp. 17-25.

S

Tabatabaei, S., see Azais, F., Jan.-Feb. 03, pp. 60-67.

Tamarapalli, N., see Lin, X., Sept.-Oct. 03, pp. 17-25.

Tamarapalli, N., see Rajski, J., Sept.-Oct. 03, pp. 58-66.

Techmer, A., see Raab, W., Jan.-Feb. 03, pp. 8-15.

Tiwari, V., see Grochowski, E., May-June 03, pp. 40-47.

Tyszer, J., see Mrugalski, G., Jan.-Feb. 03, pp. 51-59.

Tyszer, J., see Rajski, J., Sept.-Oct. 03, pp. 58-66.

U

Underwood, B., see Cory, B.D., Sept.-Oct. 03, pp. 41-45.

Unger, S.H., "Reducing Power Dissipation, Delay, and Area in Logic Circuits by Narrowing Transistors," Nov..-Dec. 03, pp. 18-24.

V

Vahid, F., "Making the Best of those Extra Transistors," Jan.-Feb. 03, pp. 96.

Van Treuren, B.G., and J.M. Miranda, "Embedded Boundary Scan," Mar.-Apr. 03, pp. 20-25.

Veidenbaum, A., see Orailoglu, A., Jan.-Feb. 03, pp. 6-7.

Vermeulen, B., see Marinissen, E.J., Mar.-Apr. 03, pp. 8-18.

Vlachos, K., see Pnevinatikatos, D.N., July-Aug. 03, pp. 56-64.

Vollrath, J.E., "Testing and Characterization of SDRAMs," Jan.-Feb. 03, pp. 42-50.

W

Wagner, K., "Arm Twisting with Sir Robin: An Interview with ARM Chairman Sir Robin Saxby," Interview,Sept.-Oct. 03, pp. 90-93.

Wahlen, O., M. Hohenauer, R. Leupers, and H. Meyr, "Instruction Scheduler Generation for Retargetable Compilation," Jan.-Feb. 03, pp. 34-41.

Wang, L.-C., see Butler, K.M., Sept.-Oct. 03, pp. 6-7.

Wheater, D.L., see Anand, D., Sept.-Oct. 03, pp. 67-75.

Wong, C.G., see Martin, A.J., Nov.-Dec. 03, pp. 9-17.

Woo Jin Kim, and Yong-Bin Kim, "Automating the Design Approach to Wave Pipelined Circuits," Nov..-Dec. 03, pp. 51-58.

Y

Yong-Bin Kim, see Woo Jin Kim, Nov.-Dec. 03, pp. 51-58.

Z

Zheng, H., L. Pileggi, and B. Kratiter, "Electrical Modeling of Integrated-Package Power and Ground Distributions," May-June 03, pp. 24-31.

Zhigang Jiang, see Quasem, M.S., May-June 03, pp. 68-77.

Zorian, Y., "Guest Editor's Introduction: Advances in Infrastructure IP," Special Infrastucture IP Section, May-June 03, pp. 49.

Zorian, Y., and S. Shoukourian, "Embedded-Memory Test and Repair: Infrastructure IP for SoC Yield," May-June 03, pp. 58-66.

Zorian, Y., see Benso, A., July-Aug. 03, pp. 32-39.

Subject Index

A
Algorithm theory;
see Computability
Analog circuits

nonlin. analog ccts., fast fault simul. Engin, N., et al., Mar.-Apr. 03, pp. 40-47.

Application specific integrated circuits

application-specific microprocessors, special section, Jan.-Feb. 03, pp. 6-41.

application-specific microprocessors, guest editor's introduction, Orailoglu, A., et al., Jan.-Feb. 03, pp. 6-7.

efficient, low-cost I/O subsystem for network processors. Pnevinatikatos, D.N., et al., July-Aug. 03, pp. 56-64.

infrastructure IP, special section, May-June 03, pp. 49-87.

infrastructure IP, guest editor's introduction, Zorian, Y., May-June 03, pp. 49.

obtaining high defect coverage for frequency-dependent defects in complex ASICs. Madge, R., et al., Sept.-Oct. 03, pp. 46-53.

Application specific integrated circuits;
see Mixed analog-digital integrated circuits
Asynchronous circuits

three generations of asynchronous microprocessors. Martin, A.J., et al., Nov.-Dec. 03, pp. 9-17.

Authorization

efficient, low-cost I/O subsystem for network processors. Pnevinatikatos, D.N., et al., July-Aug. 03, pp. 56-64.

Automatic testing;
see Automatic test pattern generation
Automatic test pattern generation

2D test seq. generators. Mrugalski, G., et al., Jan.-Feb. 03, pp. 51-59.

fault models and test generation for hardware-software covalidation. Harris, I.G., July-Aug. 03, pp. 40-47.

minimizing pattern count for interconnect test. Marinissen, E.J., et al., Mar.-Apr. 03, pp. 8-18.

Automation

automating design approach to wave pipelined circuits. Woo Jin Kim, et al., Nov.-Dec. 03, pp. 51-58.

B
Boolean algebra;
see Boolean functions
Boolean functions

Solving satisfiability in combinat. ccts. Marques-Silva, J., et al., July-Aug. 03, pp. 16-21.

Boundary scan testing

embedded boundary scan. Van Treuren, B.G., et al., Mar.-Apr. 03, pp. 20-25.

IEEE 1149.6, a boundary scan standard for advanced digital networks. Eklow, B., et al., Sept.-Oct. 03, pp. 76-83.

stds. Ashenden, P.J., Jan.-Feb. 03, pp. 91-92.

Built-in self test

2D test seq. generators. Mrugalski, G., et al., Jan.-Feb. 03, pp. 51-59.

achieving at-speed structural test. Pateras, S., Sept.-Oct. 03, pp. 26-33.

compacting test responses for deeply embedded SoC cores. Sinanoglu, O., et al., July-Aug. 03, pp. 22-30.

embedded-memory test and fix, infrastructure IP for SoC yield. Zorian, Y., et al., May-June 03, pp. 58-66.

hierarchical infrastructure for SoC test mgt. Benso, A., et al., July-Aug. 03, pp. 32-39.

power-conscious test synthesis and scheduling. Nicolici, N., et al., July-Aug. 03, pp. 48-55.

CAD;
see Electronic design automation
Circuit analysis computing;
see Circuit simulation
Circuit CAD;
see Hardware description languages
Circuit layout;
see Circuit layout CAD; Integrated circuit layout
Circuit layout CAD

design-for-verification tech. for functional pattern reduction. Chien-Nan Jimmy Liu, et al., Mar.-Apr. 03, pp. 48-55.

Circuit simulation

microarchitectural dl/dt control. Grochowski, E., et al., May-June 03, pp. 40-47.

nonlin. analog ccts., fast fault simul. Engin, N., et al., Mar.-Apr. 03, pp. 40-47.

Circuit testing

EM signatures as, tool for connectionless test. Salamati, M., et al., Mar.-Apr. 03, pp. 26-30.

minimizing pattern count for interconnect test. Marinissen, E.J., et al., Mar.-Apr. 03, pp. 8-18.

Circuit testing;
see Integrated circuit testing
Circuit theory;
see Network analysis; Network topology
CMOS integrated circuits

electrical modeling of integrated-package power and ground distribs. Zheng, H., et al., May-June 03, pp. 24-31.

Combinational circuits

Solving satisfiability in combinat. ccts. Marques-Silva, J., et al., July-Aug. 03, pp. 16-21.

Computability

Solving satisfiability in combinat. ccts. Marques-Silva, J., et al., July-Aug. 03, pp. 16-21.

Computer applications;
see Multimedia systems
Computer architecture

microarchitectural dl/dt control. Grochowski, E., et al., May-June 03, pp. 40-47.

Computer architecture;
see Parallel architectures; Reconfigurable architectures
Computer interfaces;
see System buses
Computer power supplies

microarchitectural dl/dt control. Grochowski, E., et al., May-June 03, pp. 40-47.

Computer vision

vehicle vision systs., 100-GOPS prog. proc. Raab, W., et al., Jan.-Feb. 03, pp. 8-15.

Control systems;
see Reduced order systems
Costing

bringing down NRE, The Road Ahead, Kahng, A.B., May-June 03, pp. 110-111.

embedded deterministic test for low-cost manufacturing. Rajski, J., et al., Sept.-Oct. 03, pp. 58-66.

D
Decoding

syst.-level functional verification methodology for multimedia appls. Cupak, M., et al., Mar.-Apr. 03, pp. 56-64.

Decomposition

cycle decomposition in NCLTM. Masteller, S., Nov.-Dec. 03, pp. 38-43.

Delays

clock and power gating with timing closure. Mukheijee, A., et al., May-June 03, pp. 32-39.

delay defect characteristics and testing strategies. Kim, K.S., et al., Sept.-Oct. 03, pp. 8-16.

reducing power dissipation, delay, and area in logic circuits by narrowing transistors. Unger, S.H., Nov.-Dec. 03, pp. 18-24.

speed binning with path delay test in 150-nm technology. Cory, B.D., et al., Sept.-Oct. 03, pp. 41-45.

Design aids

board-level test technologies, special section, Mar.-Apr. 03, pp. 5-39.

board-level test technologies, guest editor's introduction, Lobetti-Bodoni, M., et al., Mar.-Apr. 03, pp. 5-7.

Design engineering

automating design approach to wave pipelined circuits. Woo Jin Kim, et al., Nov.-Dec. 03, pp. 51-58.

bringing down NRE, The Road Ahead, Kahng, A.B., May-June 03, pp. 110-111.

cycle decomposition in NCLTM. Masteller, S., Nov.-Dec. 03, pp. 38-43.

delay defect characteristics and testing strategies. Kim, K.S., et al., Sept.-Oct. 03, pp. 8-16.

design and characterization of null convention self-time multipliers. Bandapati, S.K., et al., Nov.-Dec. 03, pp. 26-36.

evolution of SystemVerilog, Standards,. Rich, D.I., July-Aug. 03, pp. 82-84.

infrastructure IP, special section, May-June 03, pp. 49-87.

infrastructure IP, guest editor's introduction, Zorian, Y., May-June 03, pp. 49.

power-supply design and analysis for ICs, special section, May-June 03, pp. 5-47.

power-supply design and analysis for ICs, guest editor's introduction, Nassif, S.R., et al., May-June 03, pp. 5-6.

speed test and speed binning for DSM designs, special section, Sept.-Oct. 03, pp. 6-53.

speed test and speed binning for DSM designs, guest editor's introduction, Butler, K.M., et al., Sept.-Oct. 03, pp. 6-7.

VHDL-200X, next revision, Standards, Ashenden, P.J., May-June 03, pp. 112-113.

Design engineering;
see Design for testability
Design for testability

board-level test technologies, special section, Mar.-Apr. 03, pp. 5-39.

board-level test technologies, guest editor's introduction, Lobetti-Bodoni, M., et al., Mar.-Apr. 03, pp. 5-7.

embedded deterministic test for low-cost manufacturing. Rajski, J., et al., Sept.-Oct. 03, pp. 58-66.

PLL, catastrophic fault testing, all-digital DFT scheme. Azais, F., et al., Jan.-Feb. 03, pp. 60-67.

Digital circuits;
see Digital filters; Digital integrated circuits
Digital communication

IEEE 1149.6, a boundary scan standard for advanced digital networks. Eklow, B., et al., Sept.-Oct. 03, pp. 76-83.

Digital computers;
see Microcomputers; Special purpose computers
Digital filters

online self-fix of FIR filters. Benso, A., et al., May-June 03, pp. 50-57.

Digital integrated circuits

compacting test responses for deeply embedded SoC cores. Sinanoglu, O., et al., July-Aug. 03, pp. 22-30.

impact of low-impedance substr. on power supply integrity. Panda, R., et al., May-June 03, pp. 16-22.

Digital integrated circuits;
see Integrated memory circuits; Microprocessor chips
Digital signal processing chips

online self-fix of FIR filters. Benso, A., et al., May-June 03, pp. 50-57.

Digital storage;
see Memory cards
Digital systems;
see Digital communication
Distributed processing;
see Pipeline processing; Processor scheduling
DRAM chips

SDRAM testing. Vollrath, J.E., Jan.-Feb. 03, pp. 42-50.

Driver information systems

vehicle vision systs., 100-GOPS prog. proc. Raab, W., et al., Jan.-Feb. 03, pp. 8-15.

E
Electrical engineering computing;
see Electronic engineering computing
Electrical faults;
see Fault location
Electronic design automation

Solving satisfiability in combinat. ccts. Marques-Silva, J., et al., July-Aug. 03, pp. 16-21.

Electronic design automation;
see Circuit layout CAD
Electronic engineering;
see Electronic engineering computing; Low-power electronics
Electronic engineering computing

benefits of SoC-specific test methodology. Quasem, M.S., et al., May-June 03, pp. 68-77.

Electronic engineering computing;
see Electronic design automation
Electronic equipment testing;
see Circuit testing
Embedded systems

application-specific microprocessors, special section, Jan.-Feb. 03, pp. 6-41.

application-specific microprocessors, guest editor's introduction, Orailoglu, A., et al., Jan.-Feb. 03, pp. 6-7.

embedded deterministic test for low-cost manufacturing. Rajski, J., et al., Sept.-Oct. 03, pp. 58-66.

embedded in portable systs. on chips, design techs. Daga, J.M., et al., Jan.-Feb. 03, pp. 68-75.

embedded memories for the future, D&T Roundtable, July-Aug. 03, pp. 66-81.

embedded proc., appl.-specific instruction memory customizations. Petrov, P., et al., Jan.-Feb. 03, pp. 18-25.

interview with ARM Chairman, Sir Robin Saxby. Wagner, K., Sept.-Oct. 03, pp. 90-93.

retargetable compilation, instruction scheduler generation. Wahlen, O., et al., Jan.-Feb. 03, pp. 34-41.

Energy conservation

embedded proc., appl.-specific instruction memory customizations. Petrov, P., et al., Jan.-Feb. 03, pp. 18-25.

Energy resources;
see Energy conservation
Engineering;
see Design engineering; Maintenance engineering
Engineering computing;
see Electronic engineering computing
EPROM

embedded in portable systs. on chips, design techs. Daga, J.M., et al., Jan.-Feb. 03, pp. 68-75.

Error analysis

error tolerance, The Road Ahead, Kahng, A.B., Jan.-Feb. 03, pp. 86-87.

Error detection

error tolerance, The Road Ahead, Kahng, A.B., Jan.-Feb. 03, pp. 86-87.

Error handling

error tolerance, The Road Ahead, Kahng, A.B., Jan.-Feb. 03, pp. 86-87.

Exception handling;
see Error handling
F
Fault diagnosis

compacting test responses for deeply embedded SoC cores. Sinanoglu, O., et al., July-Aug. 03, pp. 22-30.

embedded deterministic test for low-cost manufacturing. Rajski, J., et al., Sept.-Oct. 03, pp. 58-66.

fault models and test generation for hardware-software covalidation. Harris, I.G., July-Aug. 03, pp. 40-47.

wafer-package test mix for optimal defect detection and test time savings. Maxwell, P.C., Sept.-Oct. 03, pp. 84-89.

Fault diagnosis;
see Fault location; Fault simulation
Fault location

obtaining high defect coverage for frequency-dependent defects in complex ASICs. Madge, R., et al., Sept.-Oct. 03, pp. 46-53.

Fault simulation

nonlin. analog ccts., fast fault simul. Engin, N., et al., Mar.-Apr. 03, pp. 40-47.

PLL, catastrophic fault testing, all-digital DFT scheme. Azais, F., et al., Jan.-Feb. 03, pp. 60-67.

Fault tolerance

speed binning with path delay test in 150-nm technology. Cory, B.D., et al., Sept.-Oct. 03, pp. 41-45.

Field programmable analog arrays

prog. components, digital compensation algms. Carro, L., et al., Jan.-Feb. 03, pp. 76-84.

Field programmable gate arrays

infrastructure IP for config. and test of boards and systs. Clark, C., et al., May-June 03, pp. 78-87.

reconfigurable hardware compilation. Cardoso, J.M.P., et al., Mar.-Apr. 03, pp. 65-75.

Solving satisfiability in combinat. ccts. Marques-Silva, J., et al., July-Aug. 03, pp. 16-21.

Filters;
see Digital filters; FIR filters
Finance;
see Costing
FIR filters

online self-fix of FIR filters. Benso, A., et al., May-June 03, pp. 50-57.

Formal logic;
see Boolean functions; Computability
Formal specification

syst.-level functional verification methodology for multimedia appls. Cupak, M., et al., Mar.-Apr. 03, pp. 56-64.

Formal verification

design-for-verification tech. for functional pattern reduction. Chien-Nan Jimmy Liu, et al., Mar.-Apr. 03, pp. 48-55.

Practical methodology for pipelined microarchitectures verification. Hosabettu, R., et al., July-Aug. 03, pp. 4-14.

syst.-level functional verification methodology for multimedia appls. Cupak, M., et al., Mar.-Apr. 03, pp. 56-64.

Functions;
see Boolean functions
H
Hardware description languages

design-for-verification tech. for functional pattern reduction. Chien-Nan Jimmy Liu, et al., Mar.-Apr. 03, pp. 48-55.

evolution of SystemVerilog, Standards, Rich, D.I., July-Aug. 03, pp. 82-84.

VHDL-200X, e next revision, Standards, Ashenden, P.J., May-June 03, pp. 112-113.

Hardware-software codesign

fault models and test generation for hardware-software covalidation. Harris, I.G., July-Aug. 03, pp. 40-47.

High level synthesis

FPGA-based reconfigurable hardware compilation. Cardoso, J.M.P., et al., Mar.-Apr. 03, pp. 65-75.

High level synthesis;
see Hardware-software codesign
I
IEEE standards

1149.4 analog boundary modules for enhance mixed-sig. test. Kac, U., et al., Mar.-Apr. 03, pp. 32-39.

board-level test technologies, special section, Mar.-Apr. 03, pp. 5-39.

board-level test technologies, guest editor's introduction, Lobetti-Bodoni, M., et al., Mar.-Apr. 03, pp. 5-7.

boundary scan test stds. Ashenden, P.J., Jan.-Feb. 03, pp. 91-92.

IEEE 1149.6, a boundary scan standard for advanced digital networks. Eklow, B., et al., Sept.-Oct. 03, pp. 76-83.

VHDL-200X, next revision, Standards, Ashenden, P.J., May-June 03, pp. 112-113.

Image processing;
see Computer vision
Information networks;
see Internet
Information theory;
see Decoding
Integrated circuit design

analysis and optim. of power grids. Sapatnekar, S.S., et al., May-June 03, pp. 7-15.

clock and power gating with timing closure. Mukheijee, A., et al., May-June 03, pp. 32-39.

electrical modeling of integrated-package power and ground distribs. Zheng, H., et al., May-June 03, pp. 24-31.

impact of low-impedance substr. on power supply integrity. Panda, R., et al., May-June 03, pp. 16-22.

Integrated circuit design;
see Integrated circuit layout
Integrated circuit interconnections

minimizing pattern count for interconnect test. Marinissen, E.J., et al., Mar.-Apr. 03, pp. 8-18.

Integrated circuit layout

analysis and optim. of power grids. Sapatnekar, S.S., et al., May-June 03, pp. 7-15.

Integrated circuit modeling

electrical modeling of integrated-package power and ground distribs. Zheng, H., et al., May-June 03, pp. 24-31.

Integrated circuits

achieving at-speed structural test. Pateras, S., Sept.-Oct. 03, pp. 26-33.

delay defect characteristics and testing strategies. Kim, K.S., et al., Sept.-Oct. 03, pp. 8-16.

error tolerance, The Road Ahead, Kahng, A.B., Jan.-Feb. 03, pp. 86-87.

high-frequency, at-speed scan testing. Lin, X., et al., Sept.-Oct. 03, pp. 17-25.

infrastructure IP, special section, May-June 03, pp. 49-87.

infrastructure IP, guest editor's introduction, Zorian, Y., May-June 03, pp. 49.

obtaining high defect coverage for frequency-dependent defects in complex ASICs. Madge, R., et al., Sept.-Oct. 03, pp. 46-53.

power-supply design and analysis for ICs, special section, May-June 03, pp. 5-47.

power-supply design and analysis for ICs, guest editor's introduction, Nassif, S.R., et al., May-June 03, pp. 5-6.

speed binning with path delay test in 150-nm technology. Cory, B.D., et al., Sept.-Oct. 03, pp. 41-45.

speed test and speed binning for DSM designs, special section, Sept.-Oct. 03, pp. 6-53.

speed test and speed binning for DSM designs, guest editor's introduction, Butler, K.M., et al., Sept.-Oct. 03, pp. 6-7.

Integrated circuits;
see Digital integrated circuits
Integrated circuit technology;
see Integrated circuit interconnections
Integrated circuit testing

benefits of SoC-specific test methodology. Quasem, M.S., et al., May-June 03, pp. 68-77.

compacting test responses for deeply embedded SoC cores. Sinanoglu, O., et al., July-Aug. 03, pp. 22-30.

embedded-memory test and fix, infrastructure IP for SoC yield. Zorian, Y., et al., May-June 03, pp. 58-66.

hierarchical infrastructure for SoC test mgt. Benso, A., et al., July-Aug. 03, pp. 32-39.

IEEE Std. 1149.4 analog boundary modules for enhance mixed-sig. test. Kac, U., et al., Mar.-Apr. 03, pp. 32-39.

infrastructure IP for config. and test of boards and systs. Clark, C., et al., May-June 03, pp. 78-87.

minimizing pattern count for interconnect test. Marinissen, E.J., et al., Mar.-Apr. 03, pp. 8-18.

PLL, catastrophic fault testing, all-digital DFT scheme. Azais, F., et al., Jan.-Feb. 03, pp. 60-67.

power-conscious test synthesis and scheduling. Nicolici, N., et al., July-Aug. 03, pp. 48-55.

SDRAM testing. Vollrath, J.E., Jan.-Feb. 03, pp. 42-50.

Integrated memory circuits

embedded-memory test and fix, infrastructure IP for SoC yield. Zorian, Y., et al., May-June 03, pp. 58-66.

Integrated memory circuits;
see DRAM chips
Interconnections;
see Integrated circuit interconnections
Internet

efficient, low-cost I/O subsystem for network processors. Pnevinatikatos, D.N., et al., July-Aug. 03, pp. 56-64.

Interviews

interview with ARM Chairman, Sir Robin Saxby. Wagner, K., Sept.-Oct. 03, pp. 90-93.

J
Java

reconfigurable hardware compilation. Cardoso, J.M.P., et al., Mar.-Apr. 03, pp. 65-75.

L
Large scale integration;
see VLSI
Laser beam applications;
see Laser fusion
Laser fusion

on-chip self-repair calculation and fusing methodology. Anand, D., et al., Sept.-Oct. 03, pp. 67-75.

Logic;
see Logic testing
Logic CAD;
see High level synthesis
Logic circuits

delay defect characteristics and testing strategies. Kim, K.S., et al., Sept.-Oct. 03, pp. 8-16.

reducing power dissipation, delay, and area in logic circuits by narrowing transistors. Unger, S.H., Nov.-Dec. 03, pp. 18-24.

Logic circuits;
see Asynchronous circuits; Combinational circuits
Logic devices;
see Logic circuits
Logic testing

embedded boundary scan. Van Treuren, B.G., et al., Mar.-Apr. 03, pp. 20-25.

EM signatures as, tool for connectionless test. Salamati, M., et al., Mar.-Apr. 03, pp. 26-30.

IEEE Std. 1149.4 analog boundary modules for enhance mixed-sig. test. Kac, U., et al., Mar.-Apr. 03, pp. 32-39.

infrastructure IP for config. and test of boards and systs. Clark, C., et al., May-June 03, pp. 78-87.

Low-power electronics

clock and power gating with timing closure. Mukheijee, A., et al., May-June 03, pp. 32-39.

embedded proc., appl.-specific instruction memory customizations. Petrov, P., et al., Jan.-Feb. 03, pp. 18-25.

M
Maintenance engineering

on-chip self-repair calculation and fusing methodology. Anand, D., et al., Sept.-Oct. 03, pp. 67-75.

Manufacture

AC scan path selection for physical debugging. Crouch, A.L., et al., Sept.-Oct. 03, pp. 34-40.

bringing down NRE, The Road Ahead, Kahng, A.B., May-June 03, pp. 110-111.

embedded deterministic test for low-cost manufacturing. Rajski, J., et al., Sept.-Oct. 03, pp. 58-66.

high-frequency, at-speed scan testing. Lin, X., et al., Sept.-Oct. 03, pp. 17-25.

infrastructure IP, special section, May-June 03, pp. 49-87.

infrastructure IP, guest editor's introduction, Zorian, Y., May-June 03, pp. 49.

wafer-package test mix for optimal defect detection and test time savings. Maxwell, P.C., Sept.-Oct. 03, pp. 84-89.

Mathematics;
see Optimization
Mechanical variables control;
see Velocity control
Mechanical variables measurement;
see Velocity measurement
Meetings

board-level test technologies, special section, Mar.-Apr. 03, pp. 5-39.

board-level test technologies, guest editor's introduction, Lobetti-Bodoni, M., et al., Mar.-Apr. 03, pp. 5-7.

Memory cards

embedded memories for the future, D&T Roundtable, July-Aug. 03, pp. 66-81.

Microcomputers

Practical methodology for pipelined microarchitectures verification. Hosabettu, R., et al., July-Aug. 03, pp. 4-14.

Microprocessor chips

application-specific microprocessors, special section, Jan.-Feb. 03, pp. 6-41.

application-specific microprocessors, guest editor's introduction, Orailoglu, A., et al., Jan.-Feb. 03, pp. 6-7.

delay defect characteristics and testing strategies. Kim, K.S., et al., Sept.-Oct. 03, pp. 8-16.

efficient, low-cost I/O subsystem for network processors. Pnevinatikatos, D.N., et al., July-Aug. 03, pp. 56-64.

embedded proc., appl.-specific instruction memory customizations. Petrov, P., et al., Jan.-Feb. 03, pp. 18-25.

microarchitectural dl/dt control. Grochowski, E., et al., May-June 03, pp. 40-47.

three generations of asynchronous microprocessors. Martin, A.J., et al., Nov.-Dec. 03, pp. 9-17.

Microprocessor chips;
see Digital signal processing chips
Mixed analog-digital integrated circuits

IEEE Std. 1149.4 analog boundary modules for enhance mixed-sig. test. Kac, U., et al., Mar.-Apr. 03, pp. 32-39.

PLL, catastrophic fault testing, all-digital DFT scheme. Azais, F., et al., Jan.-Feb. 03, pp. 60-67.

prog. components, digital compensation algms. Carro, L., et al., Jan.-Feb. 03, pp. 76-84.

Modeling;
see Integrated circuit modeling
Monolithic integrated circuits;
see Application specific integrated circuits
MOS integrated circuits;
see CMOS integrated circuits
Multimedia systems

syst.-level functional verification methodology for multimedia appls. Cupak, M., et al., Mar.-Apr. 03, pp. 56-64.

N
Network analysis

delay defect characteristics and testing strategies. Kim, K.S., et al., Sept.-Oct. 03, pp. 8-16.

Network analysis;
see Nonlinear network analysis
Networks (circuits)

achieving at-speed structural test. Pateras, S., Sept.-Oct. 03, pp. 26-33.

automating design approach to wave pipelined circuits. Woo Jin Kim, et al., Nov.-Dec. 03, pp. 51-58.

delay defect characteristics and testing strategies. Kim, K.S., et al., Sept.-Oct. 03, pp. 8-16.

embedded deterministic test for low-cost manufacturing. Rajski, J., et al., Sept.-Oct. 03, pp. 58-66.

IEEE 1149.6, a boundary scan standard for advanced digital networks. Eklow, B., et al., Sept.-Oct. 03, pp. 76-83.

Networks (circuits);
see Analog circuits; Integrated circuits; Phase locked loops; Phase shifters; Power supply circuits; Printed circuits; Timing circuits
Network synthesis;
see Integrated circuit design
Network topology

analysis and optim. of power grids. Sapatnekar, S.S., et al., May-June 03, pp. 7-15.

Nonlinear network analysis

nonlin. analog ccts., fast fault simul. Engin, N., et al., Mar.-Apr. 03, pp. 40-47.

Numerical analysis;
see Error analysis
O
Operations research;
see Scheduling
Optimization

analysis and optim. of power grids. Sapatnekar, S.S., et al., May-June 03, pp. 7-15.

electrical modeling of integrated-package power and ground distribs. Zheng, H., et al., May-June 03, pp. 24-31.

fault models and test generation for hardware-software covalidation. Harris, I.G., July-Aug. 03, pp. 40-47.

P
Parallel architectures

Practical methodology for pipelined microarchitectures verification. Hosabettu, R., et al., July-Aug. 03, pp. 4-14.

Parallel processing;
see Parallel architectures
Path planning

AC scan path selection for physical debugging. Crouch, A.L., et al., Sept.-Oct. 03, pp. 34-40.

speed binning with path delay test in 150-nm technology. Cory, B.D., et al., Sept.-Oct. 03, pp. 41-45.

Pattern recognition;
see Computer vision
Performance evaluation

microarchitectural dl/dt control. Grochowski, E., et al., May-June 03, pp. 40-47.

Phase locked loops

PLL, catastrophic fault testing, all-digital DFT scheme. Azais, F., et al., Jan.-Feb. 03, pp. 60-67.

Phase shifters

2D test seq. generators. Mrugalski, G., et al., Jan.-Feb. 03, pp. 51-59.

Pipeline processing

automating design approach to wave pipelined circuits. Woo Jin Kim, et al., Nov.-Dec. 03, pp. 51-58.

Practical methodology for pipelined microarchitectures verification. Hosabettu, R., et al., July-Aug. 03, pp. 4-14.

Planning (artificial intelligence);
see Path planning
Plasma inertial confinement;
see Laser fusion
Plasma production by laser;
see Laser fusion
Power distribution

power-supply design and analysis for ICs, special section, May-June 03, pp. 5-47.

power-supply design and analysis for ICs, guest editor's introduction, Nassif, S.R., et al., May-June 03, pp. 5-6.

reducing power dissipation, delay, and area in logic circuits by narrowing transistors. Unger, S.H., Nov.-Dec. 03, pp. 18-24.

Power electronics;
see Power supply circuits
Power supply circuits

clock and power gating with timing closure. Mukheijee, A., et al., May-June 03, pp. 32-39.

impact of low-impedance substr. on power supply integrity. Panda, R., et al., May-June 03, pp. 16-22.

Power supply to apparatus

power-supply design and analysis for ICs, special section, May-June 03, pp. 5-47.

power-supply design and analysis for ICs, guest editor's introduction, Nassif, S.R., et al., May-June 03, pp. 5-6.

Power systems

power-supply design and analysis for ICs, special section, May-June 03, pp. 5-47.

power-supply design and analysis for ICs, guest editor's introduction, Nassif, S.R., et al., May-June 03, pp. 5-6.

Power systems;
see Power distribution
Printed circuits

infrastructure IP for config. and test of boards and systs. Clark, C., et al., May-June 03, pp. 78-87.

Processor scheduling

retargetable compilation, instruction scheduler generation. Wahlen, O., et al., Jan.-Feb. 03, pp. 34-41.

Program compilers

application-specific microprocessors, special section, Jan.-Feb. 03, pp. 6-41.

application-specific microprocessors, guest editor's introduction, Orailoglu, A., et al., Jan.-Feb. 03, pp. 6-7.

coarse-grained reconfigurable archits., compilation tech. Jong-eun Lee, et al., Jan.-Feb. 03, pp. 26-33.

reconfigurable hardware compilation. Cardoso, J.M.P., et al., Mar.-Apr. 03, pp. 65-75.

retargetable compilation, instruction scheduler generation. Wahlen, O., et al., Jan.-Feb. 03, pp. 34-41.

Programmable logic arrays;
see Field programmable gate arrays
Program processors

application-specific microprocessors, special section, Jan.-Feb. 03, pp. 6-41.

application-specific microprocessors, guest editor's introduction, Orailoglu, A., et al., Jan.-Feb. 03, pp. 6-7.

interview with ARM Chairman, Sir Robin Saxby. Wagner, K., Sept.-Oct. 03, pp. 90-93.

Program processors;
see Program compilers
PROM;
see EPROM
Protocols;
see Transport protocols
R
Random-access storage;
see DRAM chips
Real-time systems;
see Embedded systems
Reconfigurable architectures

coarse-grained reconfigurable archits., compilation tech. Jong-eun Lee, et al., Jan.-Feb. 03, pp. 26-33.

FPGA-based reconfigurable hardware compilation. Cardoso, J.M.P., et al., Mar.-Apr. 03, pp. 65-75.

Reduced order systems

electrical modeling of integrated-package power and ground distribs. Zheng, H., et al., May-June 03, pp. 24-31.

Reliability

error tolerance, The Road Ahead, Kahng, A.B., Jan.-Feb. 03, pp. 86-87.

Reliability;
see Fault tolerance
S
Scheduling

power-conscious test synthesis and scheduling. Nicolici, N., et al., July-Aug. 03, pp. 48-55.

Scheduling;
see Processor scheduling
Security of data;
see Authorization
Semiconductor devices

AC scan path selection for physical debugging. Crouch, A.L., et al., Sept.-Oct. 03, pp. 34-40.

embedded memories for the future, D&T Roundtable, July-Aug. 03, pp. 66-81.

on-chip self-repair calculation and fusing methodology. Anand, D., et al., Sept.-Oct. 03, pp. 67-75.

speed test and speed binning for DSM designs, special section, Sept.-Oct. 03, pp. 6-53.

speed test and speed binning for DSM designs, guest editor's introduction, Butler, K.M., et al., Sept.-Oct. 03, pp. 6-7.

wafer-package test mix for optimal defect detection and test time savings. Maxwell, P.C., Sept.-Oct. 03, pp. 84-89.

Semiconductor storage;
see Integrated memory circuits
Shared memory systems;
see Vector processor systems
Shift registers

2D test seq. generators. Mrugalski, G., et al., Jan.-Feb. 03, pp. 51-59.

Simulation;
see Circuit simulation; Fault simulation
Software engineering;
see Formal specification; Formal verification
Special issues and sections

application-specific microprocessors, special section, Jan.-Feb. 03, pp. 6-41.

application-specific microprocessors, guest editor's introduction, Orailoglu, A., et al., Jan.-Feb. 03, pp. 6-7.

board-level test technologies, special section, Mar.-Apr. 03, pp. 5-39.

board-level test technologies, guest editor's introduction, Lobetti-Bodoni, M., et al., Mar.-Apr. 03, pp. 5-7.

infrastructure IP, special section, May-June 03, pp. 49-87.

infrastructure IP, guest editor's introduction, Zorian, Y., May-June 03, pp. 49.

power-supply design and analysis for ICs, special section, May-June 03, pp. 5-47.

power-supply design and analysis for ICs, guest editor's introduction, Nassif, S.R., et al., May-June 03, pp. 5-6.

speed test and speed binning for DSM designs, special section, Sept.-Oct. 03, pp. 6-53.

speed test and speed binning for DSM designs, guest editor's introduction, Butler, K.M., et al., Sept.-Oct. 03, pp. 6-7.

Special purpose computers

vehicle vision systs., 100-GOPS prog. proc. Raab, W., et al., Jan.-Feb. 03, pp. 8-15.

Specification languages;
see Hardware description languages
Standards

evolution of SystemVerilog, Standards, Rich, D.I., July-Aug. 03, pp. 82-84.

Standards;
see IEEE standards
Substrates

impact of low-impedance substr. on power supply integrity. Panda, R., et al., May-June 03, pp. 16-22.

Switching circuits;
see Logic circuits
Synchronization

Practical methodology for pipelined microarchitectures verification. Hosabettu, R., et al., July-Aug. 03, pp. 4-14.

System buses

IEEE Std. 1149.4 analog boundary modules for enhance mixed-sig. test. Kac, U., et al., Mar.-Apr. 03, pp. 32-39.

implementation of self-timed segmented bus. Plosila, J., et al., Nov.-Dec. 03, pp. 44-50.

System-on-chip

benefits of SoC-specific test methodology. Quasem, M.S., et al., May-June 03, pp. 68-77.

compacting test responses for deeply embedded SoC cores. Sinanoglu, O., et al., July-Aug. 03, pp. 22-30.

embedded in portable systs. on chips, design techs. Daga, J.M., et al., Jan.-Feb. 03, pp. 68-75.

embedded-memory test and fix, infrastructure IP for SoC yield. Zorian, Y., et al., May-June 03, pp. 58-66.

embedded proc., appl.-specific instruction memory customizations. Petrov, P., et al., Jan.-Feb. 03, pp. 18-25.

hierarchical infrastructure for SoC test mgt. Benso, A., et al., July-Aug. 03, pp. 32-39.

Systems software;
see Program processors
T
Technological forecasting

embedded memories for the future, D&T Roundtable, July-Aug. 03, pp. 66-81.

Telecommunication;
see Digital communication; Telecommunication services; Telecommunication traffic

efficient, low-cost I/O subsystem for network processors. Pnevinatikatos, D.N., et al., July-Aug. 03, pp. 56-64.

Teleconferencing

syst.-level functional verification methodology for multimedia appls. Cupak, M., et al., Mar.-Apr. 03, pp. 56-64.

Test equipment

board-level test technologies, special section, Mar.-Apr. 03, pp. 5-39.

board-level test technologies, guest editor's introduction, Lobetti-Bodoni, M., et al., Mar.-Apr. 03, pp. 5-7.

Testing

achieving at-speed structural test. Pateras, S., Sept.-Oct. 03, pp. 26-33.

AC scan path selection for physical debugging. Crouch, A.L., et al., Sept.-Oct. 03, pp. 34-40.

delay defect characteristics and testing strategies. Kim, K.S., et al., Sept.-Oct. 03, pp. 8-16.

embedded deterministic test for low-cost manufacturing. Rajski, J., et al., Sept.-Oct. 03, pp. 58-66.

high-frequency, at-speed scan testing. Lin, X., et al., Sept.-Oct. 03, pp. 17-25.

obtaining high defect coverage for frequency-dependent defects in complex ASICs. Madge, R., et al., Sept.-Oct. 03, pp. 46-53.

speed binning with path delay test in 150-nm technology. Cory, B.D., et al., Sept.-Oct. 03, pp. 41-45.

speed test and speed binning for DSM designs, special section, Sept.-Oct. 03, pp. 6-53.

speed test and speed binning for DSM designs, guest editor's introduction, Butler, K.M., et al., Sept.-Oct. 03, pp. 6-7.

wafer-package test mix for optimal defect detection and test time savings. Maxwell, P.C., Sept.-Oct. 03, pp. 84-89.

Testing;
see Boundary scan testing; Built-in self test; Logic testing
Theorem proving

Practical methodology for pipelined microarchitectures verification. Hosabettu, R., et al., July-Aug. 03, pp. 4-14.

Timing

achieving at-speed structural test. Pateras, S., Sept.-Oct. 03, pp. 26-33.

AC scan path selection for physical debugging. Crouch, A.L., et al., Sept.-Oct. 03, pp. 34-40.

delay defect characteristics and testing strategies. Kim, K.S., et al., Sept.-Oct. 03, pp. 8-16.

design and characterization of null convention self-time multipliers. Bandapati, S.K., et al., Nov.-Dec. 03, pp. 26-36.

high-frequency, at-speed scan testing. Lin, X., et al., Sept.-Oct. 03, pp. 17-25.

implementation of self-timed segmented bus. Plosila, J., et al., Nov.-Dec. 03, pp. 44-50.

wafer-package test mix for optimal defect detection and test time savings. Maxwell, P.C., Sept.-Oct. 03, pp. 84-89.

Timing;
see Timing circuits
Timing circuits

clock and power gating with timing closure. Mukheijee, A., et al., May-June 03, pp. 32-39.

Topology;
see Network topology
Traffic;
see Telecommunication traffic
Traffic information systems;
see Driver information systems
Transistors

custom functionality, making best of those extra transistors. Vahid, F., Jan.-Feb. 03, pp. 96.

reducing power dissipation, delay, and area in logic circuits by narrowing transistors. Unger, S.H., Nov.-Dec. 03, pp. 18-24.

Transport protocols

efficient, low-cost I/O subsystem for network processors. Pnevinatikatos, D.N., et al., July-Aug. 03, pp. 56-64.

V
Vector processor systems

AC scan path selection for physical debugging. Crouch, A.L., et al., Sept.-Oct. 03, pp. 34-40.

Velocity control

speed test and speed binning for DSM designs, special section, Sept.-Oct. 03, pp. 6-53.

speed test and speed binning for DSM designs, guest editor's introduction, Butler, K.M., et al., Sept.-Oct. 03, pp. 6-7.

Velocity measurement

high-frequency, at-speed scan testing. Lin, X., et al., Sept.-Oct. 03, pp. 17-25.

speed binning with path delay test in 150-nm technology. Cory, B.D., et al., Sept.-Oct. 03, pp. 41-45.

speed test and speed binning for DSM designs, special section, Sept.-Oct. 03, pp. 6-53.

speed test and speed binning for DSM designs, guest editor's introduction, Butler, K.M., et al., Sept.-Oct. 03, pp. 6-7.

VLSI

2D test seq. generators. Mrugalski, G., et al., Jan.-Feb. 03, pp. 51-59.

electrical modeling of integrated-package power and ground distribs. Zheng, H., et al., May-June 03, pp. 24-31.

impact of low-impedance substr. on power supply integrity. Panda, R., et al., May-June 03, pp. 16-22.

power-conscious test synthesis and scheduling. Nicolici, N., et al., July-Aug. 03, pp. 48-55.

VLSI;
see Wafer-scale integration
W
Wafer-scale integration

wafer-package test mix for optimal defect detection and test time savings. Maxwell, P.C., Sept.-Oct. 03, pp. 84-89.

 
 
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