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Issue No.06 - November/December (2003 vol.20)
pp: 44-50
Tiberiu Seceleanu , University of Turku
Juha Plosila , University of Turku
<p><it>Editor's note:</it>The authors propose an asynchronous structure for implementation on a SoC. An intersegment topological arrangement preserves parallelization and, through a so-called central arbiter, efficiently organizes communication with high signaling speed in the proposed structure.</p><p><it>—Fabrizio Lombardi, Northeastern University</it></p>
Tiberiu Seceleanu, Juha Plosila, "Implementation of a Self-Timed Segmented Bus", IEEE Design & Test of Computers, vol.20, no. 6, pp. 44-50, November/December 2003, doi:10.1109/MDT.2003.1246163
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