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Issue No.06 - November/December (2003 vol.20)
pp: 26-36
Scott C. Smith , University of Missouri-Rolla
Satish K. Bandapati , University of Missouri-Rolla
<p><it>Editor's note:</it> This article presents various 4-bit × 4-bit unsigned multipliers designed using the delay-insensitive null convention logic paradigm. Simulation results show a large variance in circuit performance in terms of power, area, and speed. This study will serve as a good reference for designers who wish to accomplish high-performance, low-power implementations of clockless digital VLSI circuits.</p><p><it>—Yong-Bin Kim, Northeastern University</it></p>
Scott C. Smith, Satish K. Bandapati, "Design and Characterization of Null Convention Self-Timed Multipliers", IEEE Design & Test of Computers, vol.20, no. 6, pp. 26-36, November/December 2003, doi:10.1109/MDT.2003.1246161
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