The Community for Technology Leaders
RSS Icon
Subscribe
Issue No.06 - November/December (2003 vol.20)
pp: 18-24
Stephen H. Unger , Columbia University
ABSTRACT
<p><it>Editor's note:</it> For certain asynchronous logic circuits, it's possible to reduce transistor channels at no operational cost. This technique systematically increases speed while reducing both chip area and energy dissipation. It can also improve testability. For dynamic operation, it's possible to eliminate a transistor altogether without any negative effects.</p><p><it>—Fabrizio Lombardi, Northeastern University</it></p>
CITATION
Stephen H. Unger, "Reducing Power Dissipation, Delay, and Area in Logic Circuits by Narrowing Transistors", IEEE Design & Test of Computers, vol.20, no. 6, pp. 18-24, November/December 2003, doi:10.1109/MDT.2003.1246160
19 ms
(Ver 2.0)

Marketing Automation Platform Marketing Automation Tool