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Reducing Power Dissipation, Delay, and Area in Logic Circuits by Narrowing Transistors
November/December 2003 (vol. 20 no. 6)
pp. 18-24
Stephen H. Unger, Columbia University

Editor's note: For certain asynchronous logic circuits, it's possible to reduce transistor channels at no operational cost. This technique systematically increases speed while reducing both chip area and energy dissipation. It can also improve testability. For dynamic operation, it's possible to eliminate a transistor altogether without any negative effects.

—Fabrizio Lombardi, Northeastern University

Citation:
Stephen H. Unger, "Reducing Power Dissipation, Delay, and Area in Logic Circuits by Narrowing Transistors," IEEE Design & Test of Computers, vol. 20, no. 6, pp. 18-24, Nov.-Dec. 2003, doi:10.1109/MDT.2003.1246160
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