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Three Generations of Asynchronous Microprocessors
November/December 2003 (vol. 20 no. 6)
pp. 9-17
Alain J. Martin, California Institute of Technology
Mika Nystr?, California Institute of Technology
Catherine G. Wong, California Institute of Technology

Editor's note:This article traces the evolution of Caltech asynchronous processors from a simple proof of concept, to a high-performance MIPS-like processor using a different buffer circuit for better performance, to the latest 8051 clone targeting low-energy operation. The authors describe the control aspects of the evolving circuit styles.

—Yong-Bin Kim, Northeastern University

Citation:
Alain J. Martin, Mika Nystr?, Catherine G. Wong, "Three Generations of Asynchronous Microprocessors," IEEE Design & Test of Computers, vol. 20, no. 6, pp. 9-17, Nov.-Dec. 2003, doi:10.1109/MDT.2003.1246159
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