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Issue No.05 - September/October (2003 vol.20)
pp: 46-53
Robert Madge , LSI Logic
Brady R. Benware , LSI Logic
W. Robert Daasch , Portland State University
ABSTRACT
<p><div><em>Editor's note: </em></div>Structured delay tests have been around for years, but how effectively do they identify defective silicon, even at reduced frequency? How much overkill is associated with their use? The authors present data from industrial circuits aimed at these and other aspects of speed testing.<div><em>—Ken Butler, Texas Instruments</em></div></p>
CITATION
Robert Madge, Brady R. Benware, W. Robert Daasch, "Obtaining High Defect Coverage for Frequency-Dependent Defects in Complex ASICs", IEEE Design & Test of Computers, vol.20, no. 5, pp. 46-53, September/October 2003, doi:10.1109/MDT.2003.1232256
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