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Issue No.05 - September/October (2003 vol.20)
pp: 34-40
Jason Doege , Inovys
ABSTRACT
<p><div><em>Editor's note: </em></div>Commercial EDA tools support critical-path identification, as well as transition and path delay ATPG. But how can you narrow down the target faults or paths, and which ATPG technique should you use? The authors present a practical methodology addressing these important questions.<div><em>—Ken Butler, Texas Instruments</em></div></p>
CITATION
Alfred L. Crouch, John C. Potter, Jason Doege, "AC Scan Path Selection for Physical Debugging", IEEE Design & Test of Computers, vol.20, no. 5, pp. 34-40, September/October 2003, doi:10.1109/MDT.2003.1232254
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