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Issue No.05 - September/October (2003 vol.20)
pp: 8-16
Kee Sup Kim , Intel
Paul G. Ryan , Intel
ABSTRACT
<p><div><em>Editor's note: </em></div>At-speed testing is undoubtedly critical for designs such as high-performance microprocessors. But how much of a role can structural delay testing play in testing these designs? Are speed problems caused by manufacturing variations or random defects? The authors answer these questions, using their testing experience at Intel.<div><em>—Kwang-Ting Cheng, University of California, Santa Barbara</em></div></p>
CITATION
Kee Sup Kim, Subhasish Mitra, Paul G. Ryan, "Delay Defect Characteristics and Testing Strategies", IEEE Design & Test of Computers, vol.20, no. 5, pp. 8-16, September/October 2003, doi:10.1109/MDT.2003.1232251
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