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Issue No.04 - July/August (2003 vol.20)
pp: 48-55
Nicola Nicolici , McMaster University
ABSTRACT
<p>BIST increases circuit activity and hence power in data path circuits. The voltage drop that occurs during testing causes some good circuits to fail the testing process, leading to unnecessary manufacturing yield loss. Addressing this problem, the authors show how test synthesis and test scheduling affect power dissipation and present new power-conscious algorithms.</p>
CITATION
Nicola Nicolici, "Power-Conscious Test Synthesis and Scheduling", IEEE Design & Test of Computers, vol.20, no. 4, pp. 48-55, July/August 2003, doi:10.1109/MDT.2003.1214352