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Issue No.04 - July/August (2003 vol.20)
pp: 16-21
Jo? Marques-Silva , Technical University of Lisbon
Lu? Guerra e Silva , Technical University of Lisbon
ABSTRACT
<p><div><em>Editor's note: </em></div>As EDA evolves, researchers continue to find modeling tools to solve problems of test generation, design verification, logic, and physical synthesis, among others. One such modeling tool is Boolean satisfiability (SAT), which has very broad applicability in EDA. The authors review modern SAT algorithms, show how these algorithms can account for structural information in combinational circuits, and explain what recursive learning can add to SAT.<div><em>—Marcelo Lubaszewski, Federal University of Rio Grande do Sul</em></div></p>
CITATION
Jo? Marques-Silva, Lu? Guerra e Silva, "Solving Satisfiability in Combinational Circuits", IEEE Design & Test of Computers, vol.20, no. 4, pp. 16-21, July/August 2003, doi:10.1109/MDT.2003.1214348
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