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Microarchitectural dI/dt Control
May/June 2003 (vol. 20 no. 3)
pp. 40-47
David Ayers, Intel
Vivek Tiwari, Intel

Editor?s note:

This article takes a high-level view of the power-grid noise problem as it relates to the microarchitectural definition of an IC. Through an astonishing set of simulations, the authors relate the noise problem to the details of the circuit and clocking implementation, giving insight into possible methods to reduce such noise.
--Sani R. Nassif, IBM Austin Research Laboratory

Citation:
Ed Grochowski, David Ayers, Vivek Tiwari, "Microarchitectural dI/dt Control," IEEE Design & Test of Computers, vol. 20, no. 3, pp. 40-47, May-June 2003, doi:10.1109/MDT.2003.1198684
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