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Issue No.03 - May/June (2003 vol.20)
pp: 16-22
Rajendran Panda , Motorola, Austin
Savithri Sundareswaran , Motorola, Austin
David Blaauw , University of Michigan, Ann Arbor
ABSTRACT
<p><em>Editor?s note:</em><div>Although it is tempting to think of the power grid as an independent medium of the transfer of energy from the package to the devices in the IC, some second-order technology-related effects can sometimes cause unforeseen problems. This article focuses especially on the relationship of the power delivery system to the silicon substrate properties, and shows how a low-impedance substrate can make a substantial difference in the noise generated by the power grid.</div><div>--Sani R. Nassif, IBM Austin Research Laboratory</div></p>
CITATION
Rajendran Panda, Savithri Sundareswaran, David Blaauw, "Impact of Low-Impedance Substrate on Power Supply Integrity", IEEE Design & Test of Computers, vol.20, no. 3, pp. 16-22, May/June 2003, doi:10.1109/MDT.2003.1198681
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