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Issue No.02 - March/April (2003 vol.20)
pp: 65-75
Jo?o M. P. Cardoso , University of Algarve
Hor?cio C. Neto , Technical University of Lisbon
ABSTRACT
<p>These techniques for compiling software programs into reconfigurable hardware offer faster and more efficient performance than the complex resource-sharing approaches typical of high-level synthesis systems. The Java-based compiler presented in this article uses intermediate graph representations to embody parallelism at various levels.</p>
CITATION
Jo?o M. P. Cardoso, Hor?cio C. Neto, "Compilation for FPGA-Based Reconfigurable Hardware", IEEE Design & Test of Computers, vol.20, no. 2, pp. 65-75, March/April 2003, doi:10.1109/MDT.2003.1188264
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