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A Design-for-Verification Technique for Functional Pattern Reduction
March/April 2003 (vol. 20 no. 2)
pp. 48-55
Chien-Nan Jimmy Liu, National Chiao Tung University
I-Ling Chen, National Chiao Tung University
Jing-Yang Jou, National Chiao Tung University

This technique reduces the number of required functional patterns by first defining conditions for hard-to-control (HTC) code in a hardware-description-language design and then using an algorithm to detect such code automatically. A second algorithm eliminates these HTC points by selecting a minimum number of nodes for control point insertion.

Citation:
Chien-Nan Jimmy Liu, I-Ling Chen, Jing-Yang Jou, "A Design-for-Verification Technique for Functional Pattern Reduction," IEEE Design & Test of Computers, vol. 20, no. 2, pp. 48-55, March-April 2003, doi:10.1109/MDT.2003.1188262
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