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Fast Fault Simulation for Nonlinear Analog Circuits
March/April 2003 (vol. 20 no. 2)
pp. 40-47
Nur Engin, Philips Research Laboratories
Hans G. Kerkhoff, MESA+ Research Institute

A new method of transient fault simulation uses dc bias grouping of faulty circuits and decreases the number of Newton-Raphson iterations needed to reach a solution. An experimental tool implementing this method achieves a speedup of 20% to 30% on a flat netlist.

Citation:
Nur Engin, Hans G. Kerkhoff, "Fast Fault Simulation for Nonlinear Analog Circuits," IEEE Design & Test of Computers, vol. 20, no. 2, pp. 40-47, March-April 2003, doi:10.1109/MDT.2003.1188261
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