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A Methodology for Synthesis of Data Path Circuitse
November/December 2002 (vol. 19 no. 6)
pp. 90-100

This methodology extracts the regularity of data path blocks from their HDL descriptions and preserves it throughout the synthesis process. By automating various design steps, the methodology significantly improves design productivity and achieves designs comparable in terms of delay and size to manually designed circuits.

Citation:
Amit Chowdhary, Rajesh Gupta, "A Methodology for Synthesis of Data Path Circuitse," IEEE Design & Test of Computers, vol. 19, no. 6, pp. 90-100, Nov.-Dec. 2002, doi:10.1109/MDT.2002.1047748
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