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Issue No.05 - September/October (2002 vol.19)
pp: 105-113
ABSTRACT
<p>Nowadays, designs can contain up to several hundred million transistors. Moreover, up to 80% of the over-all design costs are due to verification. Formal verification techniques provide an attractive alternative by proving the circuits? correct behavior. These techniques--for example, equivalence checking and property checking--are extensively used in many industrialflows. Difficulties with formal verification techniques include the definition and use of appropriate languages, formulation of properties, and lack of motivation of designers to use the new approaches.</p><p><em>IEEE Design & Test</em> thanks roundtable participantsJacob A. Abraham (University of Texas at Austin), AndrewBetts (Qualis Europe), Hans Eveking (Darmstadt Universityof Technology), Harry D. Foster (Verplex Systems),Thomas Kropf (Bosch), Matthew J. Morley (VerisityDesign), Thomas R. Shiple (Synopsys), and Michael Siegel(Infineon Technologies). D&T gratefully acknowledges thehelp of Rolf Drechsler (University of Bremen), our moderator;and Kaushik Roy (Purdue University), our Roundtables Editor, who organized the event. Special thanks go to the IEEE Computer Society for sponsoring the roundtable.</p>
CITATION
"Formal Verification: Current Use and Future Perspectives", IEEE Design & Test of Computers, vol.19, no. 5, pp. 105-113, September/October 2002, doi:10.1109/MDT.2002.10030
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